Claude Gauthier Ph.D., Aldo Bottelli, Ali Burney, Prashant Choudhary, Shaishav Desai, K.C. Hsieh, Haidang Lin, Chethan Rao, Socrates Vamvakos Ph.D., Alvin Wang
MoSys Inc., Santa Clara, CA
The paper explores the challenges facing designers implementing systems that are compliant to 10GBASE-KR and CEI11-LR standards. These systems can be 40-50” with multiple connectors and it is desirable to have bit-error-rates (BER) of 10-15 to 10-18 for high-reliability applications, going beyond the specification for these real-world channels. A system model is described and representative channels are presented. The paper explores the architectural and circuit techniques required to meet the stringent requirements, including the trade-offs associated with PLL implementation and receiver equalization. The LC PLL performance (<400fs) is shown to enable high-reliability system design.
The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for next generation SerDes transceivers. Not only must they handle multiple data rates to accommodate new link speeds and standards yet retain backwards compatibility for legacy systems, but they must meet tighter performance specifications to meet the challenges of the overall link design. System performance requirements come not just from the core networking infrastructure required to support Internet growth, but also from business and government demands for increasingly complex computation- and data-intensive applications such as weather prediction, financial analysis, genomics research, and design simulation.
10G-BASE-KR and CEI11-LR are two common industry specifications which have been adopted to meet these challenging bandwidth requirements. The critical electrical requirements are summarized in Table 1.
|Parameter ||10G-BASE-KR ||CEI11-LR|
|Data-rate (Gb/s) ||10.3125 +/-100ppm ||9.95-11.3|
|Interconnect ||50” + 2 connectors ||100cm+2 connectors|
|Coupling ||AC Coupled ||AC Coupled with DC optional|
|Insertion Loss at Nyquist Frequency ||25 ||--|
|Insertion Loss at Data Rate (dB) ||48.3 ||--|
|Differential Output Voltage (min/max) mV ||800/1200 ||360/770|
|Transmitter Rise/Fall times (min/max) ps ||24/47 ||24/--|
|Differential Input Voltage (min/max) mV ||--/1200 ||110/1050|
|Termination (Ohm) min/typ/max ||80/100/120 ||80/100/120|
|AC Coupling Capacitors ||100nF (Max) ||--|
|Transmit Jitter Requirements (UIpp) ||0.28 TJ, 0.15 DJ ||0.3 TJ, 0.15 DJ|
|Compliance Pattern ||PRBS-31 ||PRBS-31, CID Jitter Tolerance Pattern (CID72)|
Table 1 – CEI11-LR and 10G-BASE-KR standards summary.
The specifications define in detail what is required for electrical compliance. However some backplane systems can extend even further than the reach afforded in these standards – as far as 50” with multiple connectors. High reliability applications demand bit error rates (BER) on the order of 10-15 to 10-18.
For this paper we will consider a common backplane which meets the standard at Nyquist data-rate but is much more challenging and considered a golden-standard for compliance testing. The system consists of a Molex GbX, I-Trac backplane, with 40” trace, 2 connectors, and two 3-4” stubs. It’s is loss characteristics are shown in Figure 1.
Figure 1 – Frequency response of Molex GbX, I-Trac backplane, with 40” trace, 2 connectors, and two 3-4” stubs
Figure 2 (below) illustrates the received eye for this channel after using available transmitter equalization techniques. The eye is completely closed. This paper will describe how to design to these challenging constraints. Section 2 will describe how to build a model of the system which can be used for rigorous testing. Section 3 describes transmit techniques and highlight the importance of a quality clock source. Section 4 will address the receiver design. The paper is summarized in Section 5.
Figure 2 – Received eye after transmit equalization
II. SYSTEM MODEL
The block diagram of the SerDes architecture is shown in Figure 3. The system uses equalization at the transmitter, linear equalization and DFE at the receiver. Using just a feed forward equalizer (FFE) on the TX driver, it is theoretically possible to cancel much of the pre-cursor and post-cursor ISI, but at the cost of significant power and crosstalk. Using an analog linear equalizer in the RX, all the noise and crosstalk within the equalizer boost range will be enhanced. The discontinuities in the channel at high frequencies which may have been insignificant at lower data-rates can contribute significant noise. Crosstalk also becomes increasingly significant with both higher transitions required of higher data-rates and the higher densities in systems. Noise and crosstalk enhancement are very compelling reasons to begin using decision feedback equalization (DFE) in conjunction with traditional linear equalizers. A properly designed DFE can provide high frequency boost with little noise enhancement. The post-cursor ISI can be very many unit intervals with high insertion loss. For our architecture, we have designed the TX FFE to reduce the pre-cursor ISI, the DFE to provide high frequency boost to remove post-cursor ISI close to the cursor, and the analog LE to provide lower frequency boost which removes the post-cursor ISI further away from the cursor.
The clock data recovery (CDR) can have a very significant interaction with the DFE, as the clock can affect the samples used by the DFE which in turn will affect the phase data used by the CDR. Therefore, we have found that it is important to optimize the TX FFE in order to produce symmetrical eyes in order to obtain optimal data sampling.
Figure 3 SerDes Overview
The critical parts of the system model include:
- Transmitter equalization coefficients,
- Transmitter swing, rise/fall times
- Transmitter pad capacitance and termination
- Package and channel models, including cross-talk coefficients
- Receiver pad capacitance and equalization,
- Adaptive gain control and continuous time linear equalizer frequency characteristics
- DFE adaptation, taps and feedback coefficients
- Clock distribution characteristics
The overall view is shown in Figure 4. The capabilities of Matlab are used to optimize the design. Contour plots are computed by integrating the joint PDF of cross-talk noise and total jitter across the open eye. Contour plots are plotted at 1e-15 BER and take into account the following:
- TX RJ and DJ
- Cross-talk Noise
- RX RJ and DJ
Figure 4 Key system model components
The transmitter equalization coefficients [C-1, C0, C1] are swept from [0.0, 1.0, 0.0] to [-0.116, 0.55, -0.328]. The transmitter rise fall times are varied from 24-47ps. The transmitter conforms to the specification – deterministic jitter < 0.15UI, random jitter < 0.15UI, duty-cycle-distortion (DCD) < 0.035UI, total jitter < TJ < 0.28UI.
The cross-talk frequency response is generated using the channel insertion loss characteristics and worst-case ICR as defined in the standards as shown in Figure 5. Cross-talk is emulated by generating a colored noise sequence with the same probability-spectral-density (PSD) as the cross-talk signal.
Figure 5 Crosstalk noise emulation
The model is used to derive the CTLE parameters (gain, zero-location, boost), as well as the number of DFE taps, and determine the jitter components of the various blocks. The following sections describe the implementation of the blocks making up the system.
III. TRANSMIT PATH
The critical metrics of the transmit path are low-power, compliance to the output specifications, and most importantly, managing the transmit jitter.
To meet the system power constraints, a voltage-mode H-Bridge transmitter is used. This reduces the current consumed by the transmitter for a given swing. The 3-Tap equalization is fully programmable and the termination is accurate to within +/-5% across process, voltage, temperature (PVT).
The random-jitter (RJ) of the PLL is the most critical aspect of the transmit path because RJ cannot be tracked and the timing budgets need to account for upwards of 16-sigma for 10-15 BER. High-quality clocks are critical to achieving the specifications in real-systems. An ultra-low jitter wideband LC PLL similar to the one used in  is used to meet the exacting requirements. The block diagram is shown in Figure 5. The keys to low-jitter are the use of a supply regulator with better than 20dB of supply rejection, and the inherent spectral purity of the LC oscillator. A fractional-N divider was incorporated into the final design.
Figure 5: Block diagram of the LC PLL with VCO architecture (noise generator shown for stand-alone testing)
The measured data from the LC PLL (implemented in a 40nm process technology) is summarized in Table 2. The data validates the decision to use an LC PLL and indicates the design is well-suited to high-reliability application. A ring-oscillator PLL may approach this level of performance on a test-chip, however in a real system the noise performance often reduces the performance limiting their application in high-reliability systems. The clean clock is distributed to the transmitter using a regulated supply path.
|Random Jitter (@ 5.6GHz) ||360fs|
|Deterministic Jitter (including TX) ||980fs|
|Total Jitter ||5.97ps|
|Frequency Range ||4.5-6GHz|
Table 2 Measured data of LC PLL. The chip included 3 quads running simultaneously.
IV. RECEIVE PATH
The model (described in Section II) indicates that a 5-Tap DFE combined with a 15-20dB CTLE is required to operate the channel in high-reliability applications. The tap need not be “floating” – a fixed 5-Tap is suitable.
A 3-pole/3-zero CTLE is used with calibration logic used to adapt the CTLE. The CTLE frequency response and the equalized eye opening are shown in Figure 6. The rectangle indicates that the design has plenty of margin at low BER.
Figure 6 (a) Received eye opening indicates BER in excess of 10-18 can be tolerated, (b) CTLE response
The clock path is supply-regulated to provide a clean clock source to the receiver. Finally, to reduce the power of the design, a digital CDR is implemented.
The challenges facing designers implementing systems that are compliant to 10GBASE-KR and CEI11-LR standards were explored. These systems can be 40-50” with multiple connectors and it is desirable to have bit-error-rates (BER) of 10-15 to 10-18 for high-reliability applications, going beyond the specification for these real-world channels. A system model was described along with the critical aspects of high-reliability design including the LC PLL and receive equalization.
The authors wish to acknowledge the support of Ritesh Saraf and Sundari Mitra.
 Chethan Rao, Alvin Wang, Shaishav Desai, “A 0.46ps RJrms 5GHz Wideband LC PLL for Multi-Protocol 10Gb/s SerDes”, in Proc. Custom Integrated Circuits Conf. (CICC), 2009, pp. 239-242.