Industry Articles
Meet the SERDES challenge: Design a high-speed serial backplane-October 7, 2011 |
Michael Heimlich
EETimes (10/6/2011 9:47 AM EDT)
The benefit of having high-frequency design tools resident on a vector network analyzer (VNA) does not become obvious until the time comes to compare simulation to measurements. At this point, the advantage of a more streamlined work flow -- without the impediment of transferring data to a simulator running on a separate PC or workstation - becomes clear. To illustrate the benefit of such an
approach, this article follows the design flow for a high-speed serial backplane.
BACKGROUND: THE SERDES CHALLENGE
Increasing chip-to-chip, board-to-board, and system-to-system communications data rates have created the need for multi-gigabit asynchronous signaling schemes in which serializer/deserializer (SERDES) technology is used to format and transfer data. Analysts predict that SERDES I/O data rates will double every two to three years, so speeds in excess of 8Gb/s are already on the way and placing the SERDES design challenge clearly into the microwave domain. Consequently, designers familiar only with lower-speed buses will now be facing new physical and electrical design challenges.