Dr. Claude Gauthier, MoSys
EETimes (11/2/2011 10:36 AM EDT)
Increasingly higher-bandwidth requirements continue to drive development and demand for 40G and 100G systems. Example consumer applications include YouTube, Facebook, smart phones, and IP-TV. Governmental and business demands compound the urgency with a variety of complex data intensive solutions including weather prediction, financial analysis, genomics research, and design simulation. Further, the rapid emergence of cloud computing for both personal and business use adds additional challenges for high-volume, high complexity data transmission.
To implement these link speeds, SerDes devices must meet tighter performance specifications, with extremely high speeds running at extremely low bit-error-rates (BER). As BER trends lower, the quality of the clock source becomes critical, because the random sources of phase jitter are multiplied by scalar factors (which can exceed 16) for the purpose of link timing closure. Thus, to a large degree, the quality and performance of the link depends on the Phase-Loop Lock (PLL) circuit in the SerDes. To meet the extremely low bit error rate (BER) specifications of 10-12 and 10-15, the PLL must exhibit ultra-low jitter, on the order of sub-600fs.