Diverse IP cranks noise control headaches
Diverse IP cranks noise control headaches
By Stephan Ohr, EE Times
March 25, 2002 (10:26 a.m. EST)
If you ask designers of high-speed printed-circuit boards about signal integrity, chances are they know all about the interactions of "aggressors" and "victims" and the nasty things that can happen to logic signals clocked at near-gigahertz rates. And then there is ground bounce, noise and crosstalk-and the false triggers they can induce in logic and communications systems, where the difference between a clear signal and mush can be as small as half a decibel.
On one level, chip designers are struggling to better understand these noise issues in block-level ASIC interconnects. They have known for years how to deal with digital CMOS switching noise. What is new is the low-level hash that comes seeping up through the substrate of a mixed-signal device housing a variety of diverse intellectual-property (IP) components.
On an entirely different level, designers are wrestling with new signal integrity issues in places where they thought th ey had solved the problem. Engineers had expected to see crosstalk and impedance mismatch on poorly terminated backplanes-but not on differential signal lines like LVDS.
In this week's In Focus section, contributors tackle the problem as it appears on large complex chips and low-voltage differential-signal (LVDS) lines. IBM Microelectronics' Raminderpal Singh, director, mixed-signal and signal integrity technologies, who also co-chairs the Virtual Socket Interface Alliance's (VSIA's) working group on analog intellectual property, offers some pointers on what signal integrity issues to look for among the interconnects linking complex IP blocks. The primary author of the newly-released VSIA specification on signal integrity, he notes that next to capacitive coupling from interconnects, power grid and substrate noise should be among the biggest concerns for designers of new-generation ASICs.
Rajit Chandra, chief technologist at Magma Design Automation (Cupertino, Calif.), amplifies Singh's rema rks with an analysis of SI modeling capabilities. For interconnect modeling, thorough signoff simulation the kind you'd bet your career on must not just account for capacitive coupling. It must also include a distributed parasitic model that includes edge-rate degradation, and a "multi-aggressor" model that accounts for overlapping timing windows. Glitch analysis should include the width and height of noise pulses their accumulated energy to arrive at "less pessimistic" estimates of SI effects.
Meanwhile, manufacturers of LVDS devices National Semiconductor, Texas Instruments and Fairchild Semiconductor -come at the signal integrity problem from entirely different angles. For example, contributors Kevin Gingerich, senior member, technical staff, Texas Instruments (Dallas, Texas) and John Goldie, LVDS & SDI interface applications manager for National Semiconductor (Santa Clara, Calif.), have collaborated on an explanation of the new M-LVDS multi-point spe cification (TIA/EIA-899-2001). The standard allows a single LVDS transmitter to connect with multiple receivers without destroying the integrity of the transmitted signal. Ordinarily, LVDS specifies point-to-point transmissions on a 50-ohm line; the inclusion of multiple receivers would result in mismatched impedances and signal disruptions. The M-LVDS specification uses a somewhat higher voltage swing. The specification allows for almost a half-volt of noise as long as the lines are balanced, according to the authors.
A new wrinkle on LVDS is provided by National Semiconductor's Brian Stearns, a technical marketing engineer in the enhanced solutions group. He suggests a means of using LVDS to extend the utility of the IEEE1149.1 scan test methodology. "LVDS is a keystone for routing high-speed signals throughout the system," he writes. The scan test would provide a means of verifying the interconnect integrity of chips, boards and backplanes, while the differential signaling capability of LV DS would ensure the integrity of the test signal itself.
And, Adam Tambone, a modeling engineer with Fairchild's Interface and Logic Modeling Group (Portland Maine), offers some insights into the construction of IBIS models, the simplified input/output buffer models that have become "an important signal integrity simulation tool." The key to modeling utility, Tambone points out, is accuracy. Most IBIS models are constructed from Spice curves. This allows the models to replicate the rise-and-fall curves of LVDS signals without exposing proprietary details about the semiconductors that produce them.
For additional text and graphics on signal integrity issues go to www.planetanalog.com.
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