Allan Chin and Luciano Zoso, Stellamar
EETimes (11/8/2011 3:22 PM EST)
Programmable digital devices, led by FPGAs, have exploded in popularity as costs have come down and performance has increased. Additionally, shrinking product life cycles are making higher volumes more difficult and driving an increase in FPGA usage over ASICs. This also leads to an increase in FPGA usage in high-reliability and system-critical applications. A recent article in the EE Times, Programmable ICs: The Next Innovation Engine, identifies and describes the most fundamental challenges to continuing the growth path of FPGAs. Challenge #1 in this article is mixed-signal circuit integration. Specifically, the article mentions that ADCs, DACs, and power circuits will need to be integrated to drive the next wave of FPGA evolution.
The next wave of the FPGA evolution is further complicated because, as our end products become more complex, analog design efficiency becomes more important to the overall system. Additionally, the more sensory our end products become, the more ADCs are needed. As these end products become more portable, the efficiency of those ADCs becomes more important. Designers have often wondered if the underlying analog ADC design could ever be as efficient as digital design. Now it can be.
Originally, Stellamar set out to replicate in the ADC world what the sigma-delta DAC did for the DAC world. Most traditional DACs gave way to the sigma-delta version because of its mostly digital nature and ease of integration. This has been a much larger challenge on the ADC side. If the same could be done for ADCs, the industry would have a robust solution for the integration of ADCs into FPGAs. It was this challenge, precisely, that sparked innovation to create the most flexible, cost effective way to implement analog functions in digital fabric.
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