Mazen Khaddour, Omar Hammami (ENSTA-ParisTech)
Multi-Processors System on Chip (MPSoC) is a growing industry; studies predict the use of hundreds of processors in one system, however the impact of targeted device internal structure on the implementation of such systems has not been studied thoroughly. We developed a a Network on Chip (NoC) with Mesh of Trees topology that has been proposed in literature, this particular topology is implemented into 2 different FPGA devices the Xilinx Virtex4 and the AboundLogic Raptor 750. The Raptor FPGA has a mesh of trees as routing interconnect structure, while the Virtex 4 routing is based on a Manhattan Structure. Our paper examines the potential benefits of the correspondence in topology of logical and physical interconnect. Results shows an important boost in performance level but less gain in resources usage.
Keywords – AboundLogic Raptor 750, FPGA, Mesh of Trees, MPSoC, NoC, Virtex4.
Network on Chip is becoming the standard interconnect to be used in Multi-core and Multi- Processors System on Chip because it provides higher performance while consuming less power and less resources . Particularly because of its customizable topology it can be adapted to best suite any communication scenario between different cores. In this paper we examine the impact of targeted FPGA devices on implementation properties; the case study includes a NoC with Mesh of Trees topology [6-7] a complete shared memory MPSoC is built around this NoC and implemented onto two different FPGA Devices, the impact of targeted device has not been studied thoroughly before [2-7], we compare the effect of different FPGA global routing structures; the first FPGA has a routing based on island style structure: the Virtex4 , the second FPGA uses Mesh of Tree hierarchical Multi-Level structure: the AboundLogic Raptor 750, the second structure uses 3D Multi-layer  and provides several advantages like higher density logic, shorter delays [2-5,17] and better scalability. The paper is organized as follows: In section 2 we briefly present the routing structure of the used FPGAs, in section 3 we explain the implemented design, in section 4 we present our design methodology, in section 5 we present obtained results and finally we conclude in section 6.
II. FPGA ROUTING STRUCTURES
A. Xilinx Virtex 4 FPGA Structure
The Xilinx Virtex 4 programmable routing structure  consists of a matrix of programmable CLB
Figure1 : Virtex 4 routing structure
blocks that are connected via a number of global routing resources (wires), each CLB contains its own local routing resources and 4 slices. Each slice has 2 4-input LUT and 2 Flip Flops. 90% of FPGA area is dedicated for routing resource (wires and switch boxes). Figure 1 show global and local routing structure of the Virtex 4 FPGA B. Abound Logic Raptor750 FPGA Structure Figure 2 illustrates the Mesh of Tress Hierarchical structure of the Raptor FPGA routing interconnects that connects logical programmable elements MFC into each other to form the overall design. Where Multi-Function Cells MFC are organized into groups and groups are organized into clusters and so on, specialized units exists at different levels such as DSP48 and distributed memory units.
Figure 2: Raptor 750 Global routing structure
Local routing resources are implemented on the same plan of logical units while global routing resources are implemented on Multi-level Metal layers helping increase logical density and simplifying scalability.
III. IMPLEMENTED SYSTEM
C. Design Overview
Implemented MPSoC is presented in Figure 3 showing a MPSoC with N shared memory block units as slaves and N master PE (Processing Elements) Tiles interconnected by the Network on Chip (NoC) under test. The NoC architecture is illustrated in Figure 4, figure 4a shows the original MoT proposed in  while figure 4b shows the modified area efficient Hybrid MoT .
Figure 3: example of implemented systems; 8 PE(Processing Elements) connected to 8 shared Memory Blocks (Mem Blk)
Each PE Tile consists of a Traffic Generator to emulate a Processor activities and an OCP interfacing unit to connect to the NoC, we designed traffic generators based on NoC OCP-IP microbenchmark [8-9] in order to provide a platform
independent PE instead of using heterogeneous soft-core platform dependent processors, memory blocks contains a memory block (1Kbytes in our test), a memory controller and an OCP interface to connect to the NoC.
The used NoC topology was first proposed in  to achieve a high throughput for uniformly distributed traffic, it was modified in  to provide a more area efficient design while marginally losing performance.
Figure 4: Implemented NoC architctures
Both topologies where implemented into the two FPGA devices with various NxN master and slave numbers, Table 1 shows implemented configuration and the number of used switches to build the NoC.
Table1: Implemented Master X Slave MPSoC Configurations and number of NoC switches for both NoC Architcture
IV. DESIGN METHODOLOGY
Figure 5 shows the general flow of our design methodology for the Abound Logic FPGA
Figure 5: Design Methodology Flow for the Raptor FPGA
The same flow is vhdl files are re-used with minor platform dependent changes like memory basic blocks
Results are limited to NoC Modeling tests; Synthesis resource usages per design configuration are presented in Figure 7 with a comparison between the two devices. While maximal frequencies indicated after Place and Route are illustrated in Table 2.
Table2: Maximum Frequencies after Place and Route on Virtex 4 FX140 and Raptor750 FPGAs for different design configurations
Results show an interesting advantage for Raptor 750 FPGA of up to 40% less Flip Flops (figure 6a) and 15% less LUT (figure 6b) usage for the same design.
Figure 6: Used resources for different design configurations on Virtex4 and Raptor750 FPGAs
VI. CONCLUSION AND FUTURE WORK
We implemented various configurations of Multi- Processors with particular interconnect architecture on Abound Logic Raptor 750 and Xilinx Virtex4 FX140 FPGAs, primary results show very promising performance for the Raptor FPGA that has a similar structure to our designs architecture allowing up to 15 times faster performance, however more work is still to be done to answer fundamental questions about the impact of the particular structure of a given platform (the Raptor FPGA) on Multi-processors systems, this includes:
- Implementing a more complex and complete Multi-Processors system and evaluating it with real life applications.
- Implementing other interconnect architectures on the Raptor FPGA to evaluate the general impact of its particular structure in all case and not only in favorable situation.
- Other analysis on power and energy consumption.
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