Mike Bradley and Jon McDonald
EETimes (11/22/2011 11:02 AM EST)
A global leader in aerospace electronics needed to quantify the performance of their customers’ embedded code running on one of their delivered systems. They were able to successfully accomplish this goal by using a TLM 2.0 methodology to produce an executable system model and, subsequently, execute software to analyze functional aspects contributing to overall system level performance.
The platform they needed to analyze was a multi-board system that processes incoming data packets. Onboard timers were used to synchronize data frames and initiate CPU processing via interrupts. The CPU must process a packet before the next packet is acquired in order to maintain real time. The time from when the CPU finishes processing a packet until the arrival of the next packet is defined as CPU idle time. If enough idle time exists, then additional capabilities can be added to the system software to gain more system functionality and/or reliability. The premise of this project was that bottlenecks in the software's interaction with the hardware platform could be found and explained to the end customer, identifying potential areas for software optimization.
Previous attempts to analyze performance in the lab were not successful, due to a lack of visibility into the hardware. The challenge was that the real time nature of the application required detailed visibility of the hardware activity as the software was executing. It was not possible to stop and continue the application and get meaningful results. It was also difficult to track the details of hardware components in the physical system, such as the state and activity of the cache or the stalling effect on the processor when accessing slow peripherals. The inherent difficulty of analyzing the physical system was a major factor driving the need for a virtual prototype.
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