Thomas Anderson, Verification Product Management Group Director, Cadence
EETimes (12/12/2011 10:00 AM EST)
Formal analysis, also known as property checking, has made significant progress in the last ten years in terms of ease of use, speed, capacity, and assertion-language standardization. Formal analysis has demonstrated clear value as an important component in the functional verification of both intellectual property (IP) and system-on-chip (SoC) designs. It complements RTL “lint” checking, simulation, simulation acceleration, in-circuit emulation (ICE), equivalence checking, and other verification techniques that are more widely adopted.
The use of formal analysis is not yet as widely adopted as its advocates once predicted it would be. In part, this is because many potential users have unrealistic expectations or try to deploy formal analysis in ways that do not play to its strengths. However, thousands of users on hundreds of IP and SoC projects have used formal analysis successfully, so it is clearly possible to apply the technology in appropriate ways to improve design quality and accelerate verification schedules. Knowing when, where, and how to apply formal analysis is the key.
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