Divyesh Gajjar, eInfochips
Today there are various efficient, reusable and reliable functional verification methodologies available for Digital Design/SoC’s. Verification done using these methodologies ensures 99.99% functional correctness of Digital Design, but same does not hold true when it comes to Analog/Mixed Signal Design/SoC’s. Now due to increase in Analog Mixed Signal SoC’s/chips, there is a potential need for methodology or flow to provide similar confidence on functional verification as seen for Digital Design/SoC’s.
Some flows or methodologies being used to verify Analog / Mixed Signal Designs are mentioned below.
Method 1: Using low level non functional behavioral model.
- Digital verification: - Using current Standard verification methodologies.
- Analog verification: - Verification using circuit simulators.
- Mixed/Signal Verification: - Connectivity testing between Digital and Analog design using very low level Analog behavioral model.
Method 2: Using analog functional behavioral model developed in Verilog, VHDL or Verilog AMS language.
- Digital Verification: - Using current standard verification methodologies.
- Analog Verification: - Using spice/fast spice analog circuit simulator. Analog functional verification done using behavioral model developed in Verilog/Verilog AMS using Analog Mixed Signal simulator.
- Mixed/Signal verification: - Verification using behavioral analog model.
This paper discusses various disadvantages of methodologies currently in use. Also in this paper there is description of methodology/flow which will help to achieve complete functional verification for Analog Mixed Signal Design/SoC’s. It also provides good confidence about functional verification and correctness of Analog Mixed Signal design.
Today there are various methodologies to verify Analog Mixed Signal Verification, but they lack in ensuring 99.99% functional correctness of Design. This frequently results in re-spins of Analog Mixed Signal Design/SoCs for functional errors. Hence many companies lose time to market for Mixed Signal chips resulting into non profitable venture instead of profitable venture. Let us discuss few disadvantages seen in those methodologies.
- No logic equivalence checks between Analog schematics and behavioral model used for verification.
- No check to ensure that design used in Analog circuit simulation and behavioral model are functionally same in behavior.
- Design breaking lock up conditions: These are any lock up conditions left in design due to assumptions made during functional behavioral simulations or analog circuit simulations.
Above points show few holes or missing links seen during Analog Mixed Signal Verification. Now the question is why logic equivalence checks are needed between Analog circuit simulation and functional behavioral models. The need is, unlike digital design where RTL design used for verification is source of actual design, Analog behavioral model used for verification is not source of actual design and the Analog circuit design used as source for actual design is not verified functionally.
Methodology or flow proposed in this paper addresses above discussed missing holes or links seen in other various methodologies.
Analog Mixed Signal Verification Methodology (AMSVM) is basically divided into 4 different phases. Each Verification phase targets specific areas of Analog Mixed Signal Design Flow as shown in Figure 1.
AMSVM PHASE1: Formal Verification
This AMSVM phase targets all connectivity, combinational circuit region of design. This phase also targets connectivity testing for all voltage and current bias from various bias generators to various cells in design. It is used to verify all connectivity bugs introduced during generation of schematic or behavioral model. Verification in this phase can be done using following two different methods:-
Method1: Using Formal Verifier Tool: Create PSL or SVA assertions based on Specification. This formal check targets all connectivity and combinational circuit in design. This method does not require any test case or verification environment development.
Method2: In this method testing is done as part of functional simulation. Verification is divided into two parts.
- Design checks: These design checks verify all bias voltage and bias current values for each library cell model.
- Verification assertion to check connectivity and combinational logic.
This method requires a functional environment to generate various stimuli for design. For design checks describe in Method2 special stimulus generator is required to transmit a signature value on input voltage and bias pin, which will be checked by design checks if behavioral model is in Verilog or VHDL.
Also this phase validates that schematic and behavioral model are structurally equivalent as per specification.
This phase helps indentifying below errors in design.
- Any assumptions made during design of schematics which are violating specifications.
- Any combinational or connectivity issues in schematic design in early stage of verification. Combinational logic includes all states or values of encoder, decoder and MUX used in design.
AMSVM PHASE -2: Functional Verification.
This phase targets functional feature verification of Analog Mixed Signal design using Digital RTL and Behavioral Analog Design. Standard verification methodologies like UVM, OVM or VMM can be used to verify functional features for Analog Mixed Signal Design. Tool used in this phase of verification depends on Analog behavioral model. Analog behavioral model used here can be designed in Verilog, VHDL or Verilog AMS.
This phase verifies various aspect of Analog Mixed signal design.
- Functionality of blocks in digital and analog design.
- Various interfaces/protocols between digital and analog design.
Based on methodology used during this phase, functional correctness of design can be measured using similar parameters used for coverage driven verification (CDV). This functional correctness measurement metrics will be solely dependent on approach used for verification. It can be purely directed verification or coverage driven random verification.
At end of this phase of verification, we can ensure that all connectivity and functional features present in Analog Mixed Signal design (model) are verified as per specification.
Analog circuit simulation using “Spectre Solver” or “Fast Spice Solver” would be done in parallel to this phase of verification. There are various ways for analog circuit simulation (not covered here as our target is to achieve functional correctness using this methodology). Analog circuit simulation mainly targets optimization of circuit parameters and various performance parameters like power, current, frequency, speed, yield, etc.
AMSVM PHASE -3: Logic Equivalence Check
Above 2 phases verify that Analog Mixed Signal Design is functionally correct, but they do not ensure that analog spice/spectre netlist used for analog circuit simulation is functionally equivalent to Analog behavioral model. Also they do not check that any assumptions made during circuit simulation of mixed signal design or generation of Analog behavioral model is not creating any lock up conditions for Analog Mixed signal Design.
During this phase Analog Behavioral model is replaced by Analog spice/spectre netlist in verification environment used during AMSVM Phase 2. Few small tests exercising basic functional paths of design are run in this environment. Here pass fail criteria for test can be determined based on following two methods:-
- Self checking directed tests.
- Post processing of simulation output results.
Both HDL and Fast Spice simulators are needed to run mixed signal simulation in this phase. For example Cadence: IUS and Virtuoso (ultrasim).
Test case used during this simulation should be short as mixed signal simulation is very slow. Spice/spectre netlist should be generated with minimum required parameters or depth of extraction to reduce the simulation time. Using same environment and test case here gives a better confidence to design and verification team about functional correctness and stability of the design. It also ensures logic equivalence check between analog spice netlist used for analog circuit simulation and analog behavioral model. This stage ensures that functionally verified design is really used for Physical design layout and floor plan. This phase does same kind of verification as logic equivalence check (LEC) done between Digital RTL and Digital Gate Netlist.
Disadvantage: It depends on test list determined by design and verification team, whereas in case of Digital, it is automated testing using EDA tool. So quality of this verification solely depends on completeness of test list.
AMSVM PHASE – 4:
During this phase gate level simulation with SDF is run on post routed Digital and Analog netlist. A common question that arises in everyone’s mind is why we need gate level simulation with SDF on post routed netlist, as we already do LEC for digital design and STA for both analog and digital design so this phase normally looks redundant.
If by mistake designer has placed a timing exception like false path and multi-cycle path then it won’t be caught. Normally we have different designers for Analog and Digital team, so there may be chances that some assumption made for analog to digital or digital to analog handoff for timing may be wrong. This gate level simulation with SDF on post routed netlist is to counter check for STA and to catch mistakes the designer has made on placing any timing exceptions.
Below Table 1 shows tools required for Analog Mixed Signal Verification Methodology (AMSVM)
| ||Formal Verifier Tool ||Functional Verification Tool ||AMS Simulator ||Analog Circuit Simulators (spice, spectre , fast spice)|
|AMSVM Phase 1- Method 1 ||YES ||YES ||NO ||NO|
|AMSVM Phase 1- Method 2 ||NO ||YES ||NO ||NO|
|AMSVM Phase 2 – Analog Behavioral model in Verilog or VHDL ||NO ||YES ||NO ||NO|
|AMSVM Phase 2 – Analog Behavioral model in Verilog/VHDL AMS ||NO ||YES ||YES ||NO|
|AMSVM PHASE 3 ||NO ||YES ||NO ||YES|
|AMSVM Phase 4 – Analog Behavioral model in Verilog or VHDL ||NO ||YES ||NO ||NO|
|AMSVM Phase 4 – Analog Behavioral model in Verilog/VHDL AMS ||NO ||YES ||YES ||NO|
Table 1: List of tools required for different AMSVM phases.
During any Analog Mixed Signal project we required HDL Simulator to simulate Digital portion of design and Analog Circuit simulator for Analog design. If Method 2 is AMSVM Phase- 1 and Analog Behavioral model is designed using HDL languages like Verilog /VHDL. There is no additional cost in project for tools. There may be a question arising when same verification results can be achieved using both methods shown in AMSVM Phase -1, then why 2 methods are described. It is true that results achieved are same, but with Method1 it takes less verification effort/time to achieve those results. So depending on project schedule and cost, it can be decided whether to use Method1 or Method2.
CASE STUDY RESULT:
For a 1.6Gbps Timing Generator Analog Mixed Signal ASIC project in 0.13um CMOS, Analog Mixed Signal Verification Methodology (AMSVM) was used.
AMSVM PHASE-1: verification was done by developing model to test all analog signals using signature values and System Verilog Assertions (SVA) to check connectivity and combinational logic. AMSVM PHASE- 2: Functional verification was done using CDV (Coverage Drive Verification) approach. Functional environment was developed using reusable UVM methodology.
During AMSVM PHASE-3: Ultrasim (Fast Spice) solver was used during mixed signal simulation. Average mixed signal simulation time was-:
1 hour =~ 170 ns
Tools: Cadence: IUS, Virtuoso (Ultrasim)
Majority of connectivity bugs for bias voltage, current and other analog pins were caught during AMSVM PHASE-1 and early part of AMSVM PHASE-2. As majority of connectivity issues were caught earlier, it had reduced the time to debug such failures during Analog circuit simulation. AMSVM PHASE -3 caught few critical lock up conditions which were present during initial power up sequence of the chip. AMSVM PHASE-4 caught few handoff timing issues resulting in functional failures.
Below Table 2 shows bugs found during various phases of Analog Mixed Signal Verification.
|Analog Mixed Signal Verification Phases ||No of bugs found|
|AMSVM PHASE -1 ||33|
|AMSVM PHASE -2 ||71|
|AMSVM PHASE -3 ||6|
|AMSVM PHASE -4 ||11|
Table 2: Summary of bugs found during various AMSVM Phases.
Through applying this methodology, majority of functional errors are caught in first 2 verification phase’s i.e. early part of verification. This results in saving significant amount of time in Analog circuit simulation. Also major lock up conditions caught in phase 3 are detected during initial bring up of chip, that helps avoiding cost of re-spin because of such issues.
A methodology proposed provides complete functional verification for Analog Mixed Signal Design with following advantages:-
- It helps to reduce time to market and cost for Analog Mixed Signal ASIC/SoC’s by catching bugs in early stage of verification.
- It helps catching bugs which normally go undetected due to missing links in verification.
- Like Digital Functional Verification, it provides 99.99% functional correctness of Analog Mixed Signal Design.