Sandeep Bhatia, Senior R&D Director, Oasys Design Systems
EETimes (2/16/2012 12:43 PM EST)
Designers relate to Design for Test (DFT) in much the way that small children relate to scary programs on TV: if they cover their eyes with their hands, perhaps it will go away. But every designer also knows that the design that they are so lovingly bringing into existence won’t see the light of day without addressing the test problem. After all, every single chip needs to be tested.
These days, there is a growing realization that DFT is evolving and, in particular, is not something that can be left to the end of the design cycle when some resident test expert lays his or her hands on the design and pronounces it good. We have all heard far too many stories of the last-minute chaos, and the inevitable schedule slips, that come from leaving test as an after thought. DFT in a modern design requires a systematic approach to planning early on.
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