Dhrubajyoti Kalita, Intel
EETimes (2/21/2012 10:38 AM EST)
Today’s SoC verification environments require a reusable verification IP (VIP) infrastructure that allows plug-and-play of verification IP in SoC integration. The VIP must include hooks in the verification IP that would make writing an SoC integration test environment (tests, BFMs, monitors, checkers) easier and faster. Typically, SoC verification methodologies focus on verifying only the glue logic of the reused IP, rather than verifying IP functionality in the SoC environment.
The current verification IP landscape comprises multiple implementation languages: C, C++, SystemC, VHDL, Verilog, SystemVerilog, ‘e’, OpenVera, etc. Although SystemVerilog is the unifying standard, legacy use of other languages lingers as IP vendors adopt SystemVerilog. Every VIP brings unique challenges to integration with the SoC environment, such as synchronizing SystemVerilog test sequences with SystemC/C/C++ code. The solution is often VIP specific and takes significant effort to implement. Moreover, because SoC verification environments need to stitch all the heterogeneous VIPs together, which is often a painful process, maintaining the SoC environment is resource intensive as well.
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