Marc Greenberg and Samta Bansal, Cadence
EETimes (2/22/2012 1:21 PM EST)
The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512-bit data interface, JESD229 Wide I/O Single Data Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.
Devices that use TSV connections between homogeneous dice are already available. Wide I/O is leading the way to TSV connections between heterogeneous dice.
Among the companies offering devices with homogeneous TSV connections are Xilinx, whose Virtex-7 2000T field-programmable gate arrays use logic connected to logic, and Samsung, whose 32-Gbyte registered dual-in-line memory modules (RDIMMs) use DRAM stacked with DRAM. There are many good reasons for homogeneous TSV connections. Xilinx claims its devices offer a hundredfold improvement in die-to-die connectivity bandwidth per watt with one-fifth the latency; Samsung claims a 40 percent reduction in power.
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