English
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Adjusting and calibrating out offset and gain error in a precision DAC
David Fry, Strategic Applications Manager, Maxim Integrated Products
EETimes (3/23/2012 4:05 PM EDT)
All digital/analog converter (DAC) systems experience gain and offset error. These are analog errors caused by many factors in the DAC and in the external signal path. Gain and offset error should, therefore, be specified in the data sheet for a precision DAC.
This application note describes these DAC errors and their sources, and then describes methods for calibrating out that error in both the analog and digital domains.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- The Future of Embedded FPGAs - eFPGA: The Proof is in the Tape Out
- Out of the Verification Crisis: Improving RTL Quality
- A MAC-less Neural Inference Processor Supporting Compressed, Variable Precision Weights
- Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
New Articles
- Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers