Christian Caillon, C Cube Hightech
EETimes (4/5/2012 1:19 PM EDT)
Reducing the power consumption of electronic equipments is becoming a key differentiator for performances and costs. It is obvious for portable equipments such as smartphones or tablets but also for devices such as set top boxes or TV where thermal problems can occur if power consumption is not well managed. It is really a big challenge for system architects and IC designers to meet the power budget provided by the OEM’s specifications and to make early decisions to manage power. The power reduction methods such as clock gating, power gating, memory gating, DVFS, multi-Vt, transistor dynamic body biasing are now well known but the problem is how to optimize the use of this set of techniques to surely reach the power budget and device specifications. On top of that, engineering time and global effort provided by engineers to meet power specifications is growing with system complexity impacting the time to market. It can be considered that 25% of time is spent by engineers to work on power reduction techniques and analysis. Due to the convergence of multiple applications in smartphones and tablets (telecommunications, internet, games, and multiple connectivity protocols) we can also observe that each new generation of equipment is introducing more complex use cases multiplying the number of power management scenarios.
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