4/5/2012 1:59 PM EDT
A closer look at the Kintex-7 FPGA
TMSC's HPL NMOS and PMOS transistors, as seen in the Kintex-7 FPGA, are shown below. The two transistors are made using a gate-last process, where the TiN/HfO2/oxide gate dielectric is first deposited, followed by the deposition, patterning and etching of the sacrificial polysilicon gates. Silicon nitride sidewall spacers are then formed along the sides of the gates and are used to define the source/drain regions.
The sacrificial polysilicon gates are then removed and different gate metals are deposited into the NMOS and PMOS gate regions. The bottom portions of the metal gates include the work function metals, TiAlN for the NMOS and TiN for the PMOS transistors, as can be seen in the TEM images.
And perhaps as a nod to cost savings, TSMC has eschewed strain engineering to boost the transistors’ performance. Instead, rotated wafers are used that place the transistor channels in a <100> orientation to boost the PMOS drive current. This avoids the need for embedded SiGe PMOS source/drain regions used by Intel (and by TMSC’s HP) process. (Note: The <100> refers to a direction in the silicon lattice, in this case the direction of the current flow through the channel of the transistor.)
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