Arvind Shanmugavel, Apache Design
EETimes (5/7/2012 10:06 AM EDT)
The design and implementation process for integrated circuits (ICs) has been honed and perfected for decades by the design and the electronic design automation (EDA) community. However, the reliability verification process has been slow to catch up, especially due to the complex nature of failure mechanisms. Chip designers in the past were willing to take risks when it came to reliability verification because it was not seen as a functional failure or something that caused yield fallout. But times have changed and the EDA and simulation software community has swiftly responded to the needs of a simulation driven reliability analysis model. This article will delve into what it takes to design for reliability today.
Over a decade ago, the IC design and verification process would include design margin for almost every form of physical verification. Margins were added for several checks such as timing, IR drop, decap requirements, etc. Essentially, these margins were built-in to the verification sign-off process because the true operating condition could not be modeled accurately. For example, the voltage drop at the full-chip level was only simulated using a static analysis. Both tools and compute power were not adequate enough to simulate the entire chip, package, and system in a transient analysis. Design margins were built into a static IR drop analysis to account for dynamic behavior. Another example is the case of timing sign-off. Margins for set-up and hold times were built-in to account for voltage drop effects and aggressor-induced slow down or speed up of interconnect delays. Reliability verification such as electro-migration and self-heat were typically done with worst case switching, temperature, and recovery factors. There was no clear way to achieve realistic switching behavior, or a realistic die temperature profile when signing off electro-migration and self-heat effects.
Fast forward to today, the age of simulation-driven product design. Every IC designer has a toolbox of EDA products to help simulate and verify various reliability phenomena. Reliability verification for ICs not only covers classic electro-migration and self-heat, but also verification of power / ground noise verification, substrate noise, thermal reliability, electro-magnetic interference (EMI) and electrostatic discharge (ESD) events.
Multi-physics modeling such as electro-magnetic, thermo-mechanical, electro-mechanical and thermo-electric are mature in the simulation industry, albeit still evolving. Failure mechanisms in ICs are caused by one physical phenomenon affecting another. For example, the effect of temperature on the electrical resistance of wires, or the effect of current flow on heat dissipation in wires (joules heating), are both thermo-electric multi-physics phenomena. Other examples include the impact of temperature on IC mechanical failures and electro-magnetic interference between multiple ICs in a system. Simulation tools no longer analyze one phenomenon in isolation. They are able to seamlessly straddle different domains of analysis in order to model the true behavior of the system. Multi-physics principles and complex model exchanges are being used to simulate failure mechanisms.
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