Uri Tal, Rocketick
EETimes (5/3/2012 12:11 PM EDT)
Graphic Processing Units (GPUs) hold great promise in the field of high-performance-computing (HPC). Having immense computational power and high memory bandwidth packed in a commoditized hardware platform, GPUs have already been successfully utilized by oil and gas companies, and computational finance and similar organizations seeking the best compute-bang for their bucks. EDA applications have a lot in common with other HPC applications – huge quantities of computations and memory-related operations.
EDA applications have been traditionally implemented on regular processors. Most, if not all, of these applications were not designed for parallel or vector processors. For example, HDL simulators, being event-driven, manage a single queue of events and handle events one at a time, serially. To be able to utilize a massive multi-core architecture, it is not sufficient to even completely rewrite the software; the algorithms must be re-thought with parallelism at the heart of the process.
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