Carey Robertson, Mentor Graphics
EETimes (5/10/2012 9:07 AM EDT)
Whether you are migrating to 20nm processes, considering the migration, or just watching the fireworks, you no doubt understand that there are profound issues to consider for physical design and implementation. Double-patterning (DP) is driving new design requirements, and if you’ve been following any of the industry discussion, you know that words such as “coloring,” “colorless,” “cutting,” “stitching,” and “anchoring” are now part of the vocabulary for 20nm design. With 20nm and DP, we have geometries on the same layer being produced by different masks. This shift in silicon manufacturing changes the requirements for physical design—which means design methodologies, design tools, and verification tools must evolve to ensure we can continue producing robust designs within these new constraints.
Much of the discussion so far has addressed the physical impact of DP, but what will be the electrical impact? Consider the dilemma for the circuit designer implementing a differential pair at 20nm. Even at older technologies, the designer adheres to strict methodologies to ensure symmetrical electrical performance—wire lengths and widths must be matched, and device widths and lengths must be identical. At 28nm, poly-to-poly spacing, proximity of the device to the well, and the lengths of diffusion must also match up for the circuit to perform correctly. At 20nm, wires placed on different masks could experience slightly different process variations, resulting in a slightly different proximity to their neighbors. Designers will not only have to be diligent about keeping symmetric wires on the same mask, but will also have to pay close attention to the orientation of those geometries to which that circuit has coupling capacitance.
Let’s discuss the electrical impact of 20nm processes, and some of the techniques that can be used to mitigate performance issues.
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