Mayank Verma and Vijay Bhargava, Freescale Semiconductor
EETimes (5/30/2012 2:51 PM EDT)
When designing an SoC with a generic 32-bit MCU based on 0.18um (180 nm) processes with flash and a rich suite of analog and digital IPs, the authors found that the pre-route engines from current EDA tool vendors are tuned for smaller transistor node sizes and are not very good at the larger 180 nm geometries. Here are the steps they took to overcome such problems.
With the emergence of newer and faster technologies, we have seen a rapid increase in the number of complex designs that push CMOS transistor geometries to 90 nm and smaller dimensions. But designs based on larger dimensions are not disappearing. In fact, process technology nodes with 180nm and 250nm geometries are still considered “hot".
If you consider yourself well equipped with the latest 90 nm EDA tool in your kitty, assuming it will be just as efficient at relatively conservative technology nodes such as 180nm, you might be in for a surprise. More so if the so-called “small design” requires seamless backward package-pin compatibility, has high frequency requirements, and targets fierce gross-margin numbers.
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