ACE'ing the verification of a cache coherent system using UVM

Peer Mohammed (MindSpeed Technologies), Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma & Satyapriya Acharya (Synopsys)
EETimes (6/25/2012 10:54 AM EDT)

The AMBA 4 specification for the connection and management of functional blocks in a system-on-chip (SoC) now features Advanced eXtensible Interface (AXI) coherency extensions (ACE) in support of multi-core computing. The ACE specification enables system-level cache coherency across clusters of multi-core processors. When planning the functional verification of such a system, these coherency extensions bring their own complex challenges, such as system-level cache coherency validation and cache state transition validation. At any given time, it’s important to verify that the ACE interconnect can maintain cache coherency across the different ACE masters in the system. Cache state transition validation involves verifying the ability of the ACE interconnect to handle all cache line state transitions in ACE masters in the system. This requires a high degree of configurability and responsiveness in the stimulus generation infrastructure, as well as a robust checking mechanism for validating the system-level cache coherency.

This article will describe how the Universal Verification Methodology (UVM) configuration mechanism can be leveraged to optimize configurability of the sequences. This mechanism also enables the reactive sequences to create the right stimulus for the respective CIP (Master/Slave/Interconnect) components. Given that coherency has to be maintained across multiple masters, this must enabled through the system and sub-system-level components. By using the UVM resource mechanism and ACE interconnect in different modes (active/passive), the cache coherency can be checked via a combination of front-door and backdoor accesses. The UVM hierarchical phasing schemes and configurable sequences can also be leveraged to model various transitions for the system to ensure complete verification closure. To handle such a complex system, an appropriate debug environment is also described, allowing the verification engineer to debug the environment at different levels of abstraction using the base UVM infrastructure.

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