Florian Mueller, Fujitsu Semiconductor Europe (FSEU)
EETimes (7/20/2012 6:20 PM EDT)
High-resolution graphics displays are becoming a key part of automotive manufacturers' strategies to simultaneously differentiate from their competitors, reduce production cost, and increase customer satisfaction. Our group at Fujitsu develops IP blocks and SoCs to help customers realize these advantages.
One of our IP blocks is called Iris, a 2D graphics engine. This IP is composed of many reusable sub-components, which can be easily rearranged to create new derivatives of Iris that are then integrated into a range of products. All of these sub-components, of course, need to be verified in addition to the final product. For this purpose, we employ a metric-driven verification flow.
Traditional approach
In the usual implementation of metric-driven verification, all the stakeholders of the IP (software, hardware, design and verification engineers) define a verification plan that specifies what needs to be done so that they all can agree on signing off the IP for tapeout. The plan contains a number of items (what needs to happen, targets the stimuli/design inputs), a number of checkers (what needs to be checked, targets the design outputs), and maybe also a number of directed tests for corner cases internal to the design.