Adnan Hamid - Breker Verification Systems
EETimes (8/13/2012 3:56 AM EDT)
As system-on-chip (SoC) designs have become ever more complex, verification engineers have risen in importance to become an integral part of a product’s success. With more SoCs being designed, there is a growing class of verification engineers who are woefully under-appreciated in terms of the complexity of the job they have to do and the lack of tools made available to them. These are the engineers given the responsibility for integration verification as well as system verification and validation.
This article defines the unique problems that SoC verification engineers face in their jobs and outlines an approach that provides a level of automation for them similar to that enjoyed by block-level verification teams. It also discusses longer-term implications of this approach within the overall SoC development flow and demonstrates that a higher level of abstraction is necessary for efficient and effective verification.