Reshmi Ravindran, Cypress Semiconductor
EETimes (9/17/2012 3:36 PM EDT)
Part 1 of this article discussed the hardware aspects required for interfacing QDRII+ memory with an FPGA. Part 2 deals with implementation of the QDR II+ controller in popular FPGAs using standard IP blocks.
Implementation of memory interfaces on FPGAs, especially for high-speed memories, was a tedious process until most of the FPGA vendors started providing configurable memory controller IP, such as the Xilinx Memory Interface Generator (MIG) tool and Altera’s QDR controller Megacore functions. These IP libraries are expensive and are not available with all variants of the FPGAs, however. Fortunately, alternatives exist. Most high-speed FPGAs offer standard IP blocks that can be configured and integrated to build a custom memory controller. This enables designers to develop memory controllers for their application and allows them to customize it suitably. Understanding the timing diagram of QDRII+ is essential for the controller implementation. Let’s take a closer look.