Naman Gupta - Freescale Semiconductor
10/1/2012 10:29 AM EDT
Timing defines the performance of a chip. If timing constraints are not met, the chip is as good as dead. Any extra pessimism in timing analysis not only requires more time to fix the critical paths but could negatively impact other important parameters such as power and area. In the worst case, it might leave no option but to reduce the functional frequency of the design. On the other hand, optimism in timing analysis might result in silicon failure. Finding a bug in silicon can be a ponderous task, not to mention the monetary and goodwill loss for design companies. It is therefore prudent to remove undue pessimism and optimism from timing analysis.
Clock architectures have become fairly complex for modern SoCs. In synchronous design, clock controls the switching of sequential elements of the design and functionality of logic is ensured through meeting the required setup and hold checks. Timing engineers must remove any undue pessimism/optimism in the calculation of clock path delay because it can be detrimental for the design.
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