Fabio Giovagnini and Antonio Di Marzo, SESM S.C.A.R.L.
EETimes (10/2/2012 5:54 PM EDT)
Partial dynamic reconfiguration is a radical new way to configure and reprogram an FPGA. Unlike the standard FPGA reconfiguration process, PDR allows you to change a small part of the device based on the needs of your design, while other parts are still running. There is no need to hold the device in reset while an external controller or internal piece of glue logic reloads a design onto it, the standard reconfiguration methodology. With PDR, critical parts of the design continue operating while a controller, either on or off the FPGA, loads a partial design into a reconfigurable module. The technique pays off in hardware resource optimization and a reduction in power consumption.
The PDR method has emerged as a topic for investigation in the context of the European Union research project pSHIELD. This project aims at pioneering techniques to build security, privacy and dependability (SPD) into embedded systems, rather than tacking them on as “add-on” functionalities. The idea behind pSHIELD is to take a first step toward SPD certification for future embedded systems. The leading concept is to demonstrate the composability of SPD technologies.
In such a context, we have identified PDR as a key technology to implement a secure, dependable and reconfigurable embedded system. Our investigation of this new technology involved implementing a project demonstrator—a reconfigurable frequency shift-keying (FSK) demodulator system—within the Xilinx PDR design flow.
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