David White, Cadence Design Systems
EETimes (10/29/2012 9:01 AM EDT)
One of the biggest challenges in analog/mixed-signal IC design is uncertainty in electrical behavior and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced nodes that will be needed to meet demands in high-growth areas like mobile computing. In conventional custom IC design flows, there is little observability into the electrical impact of physical design decisions until the layout is complete and design intent can be verified through parasitic extraction and circuit simulation. The combination of electrical uncertainty combined with increasing sensitivity of AMS designs to parasitics and layout dependent effects can result in significantly higher turn-around times and more conservative designs that sacrifice performance for reliability. To mitigate the risks associated with moving to advanced nodes, IC design teams will require EDA solutions that reduce electrical uncertainty and ensure design intent is preserved during custom design.
An ideal solution would electrically verify the performance and reliability of every single physical design decision so the layout is electrically correct by construction and optimized to meet the design intent. This article describes a new EDA methodology, called electrically-aware design, where every physical design decision regarding placement and routing can be analyzed or visualized in terms of its impact on electrical performance and reliability. While this methodology can be applied to a number of use models, this article focuses on reducing the uncertainty associated with electromigration (EM)-related reliability, an increasingly serious problem at advanced process nodes.
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