Implementing configurable logic blocks on a microcontroller IC is by now an established practice. These blocks in the past have been implemented either as register-configured fixed logic or as an array of programmable-logic cells. But in a recent chip design Cypress Microsystems, a division of Cypress Semiconductor Corp., undertook to create a flexible, user-configurable portfolio of moderate-performance analog and mixed-signal functions on an MCU die. These functions were to exist in addition to, and work in concert with, a set of user-configurable digital function blocks to form a complete mixed-signal MCU system-on-chip.
The design started with a process capable of implementing the precision passive components needed for the design. This process provides both resistors and metal-to-metal capacitors, the latter using a special dielectric material. It also includes flash memory capability, but flash cells are not used in the analog section of the d ie. Remarkably, the process, developed internally at Cypress Semiconductor, layered the flash and analog capabilities on top of a standard digital CMOS process, using only about three-quarters as many mask steps as a comparable process from a major foundry.
With the process in hand, it was necessary to develop a collection of analog components, organize them in a way that made implementation of commonly used analog and mixed-signal functions practical, and implement the design on an MCU die.
The analog array
The design was pursued in an iterative fashion, starting with a basic idea of what components would go into the analog blocks and what functions we wished to implement in the resulting chip. It was determined that an analog block would include two amplifiers, a collection of resistor and capacitor networks, and the analog switches necessary to configure these components into working subsystems. In addition, the blocks would have to include the underlying decode logic and configuration r egisters to control the analog switches.
The objective was to permit designers to implement either of two design styles: continuous-time circuits using the amplifiers and resistive networks, or switched-capacitor designs using the amplifiers and capacitor networks.
A first-pass design of the analog block determined rough area, interconnect flexibility and cost. This design was compared against the various functions we wished to be able to implement in the configurable blocks, and the process was iterated to produce an analog block design that implemented the widest variety of possible functions in the least area. These functions, it should be noted, ranged from relatively simple amplifiers and filters to delta-sigma modulators-devices that proved quite challenging.
The resulting design emerged as an orderly array of components including the two amplifiers, a comparator, resistor networks and three networks of 32 binary-weighted capacitors.
Our team now confronted one of the most difficult challenges in the design: creation of the amplifiers. The team laid out the amplifiers, as well as the passive components in the array, by hand. Then the controlling digital circuitry was automatically placed and routed. Since much of the digital circuitry-the part not involved in controlling switched-capacitor networks-was static except during configuration, noise issues between the digital and analog portions were eased somewhat.
One of the most serious issues that emerged from the detailed design was the interconnect topology within the analog array. We had hoped to rely primarily on nearest-neighbor connections between elements in the array. It was clear from the outset that we could not afford the overhead of enough interconnect and switches to provide connection between arbitrary elements in the array. By continuously refining the array topology and, at the same time, the implementations of the user functions we wished to offer, we were able to converge on an interconnect scheme that met our needs within our budget.
After this design and analysis process, we were delighted when the first tapeout of the array proved fully functional. We were considerably less delighted when we discovered that the die had serious noise issues. Further analysis indicated that the RC extraction tool we had initially used, Vampire, lacked the accuracy to cope with the rather extreme sensitivity our circuits exhibited to capacitive coupling. We learned that 1 or 2 femtofarads of coupling at the wrong spot were capable of causing relatively huge linearity issues in data converter designs.
Fortunately, by this time more advanced extraction tools were available. Using Cadence Assura and applying guard shielding to critical nets, we were able to achieve our specifications.
--- Warren Snyder, who is chief technical officer at Cypress Microsystems (Bothell, Wash.), developed the M8 microcontroller core used in all of Cypress' USB controllers. Snyder received an MSc degree in computer engineering from Simon Fraser University (Burnaby, British Columbia).
Copyright © 2002 CMP Media LLC
5/1/02, Issue # 14155, page 12.