Integrating Radios Needs Fine-Tuning

Integrating Radios Needs Fine-Tuning
By Jim Wight, Integrated System Design
May 3, 2002 (9:10 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020430S0044

The integration of RF into single-chip devices is an ongoing challenge. A strategic plan should be developed based on what to integrate and when. This article offers a strategy for implementing the integration in a timely fashion.

To maximize performance, traditional radio designs incorporate key circuit components. Among these are gallium-arsenide-based power amplifiers (PAs) and transmit/receive (T/R) switches, ceramic-based RF filters, high-temperature co-fired ceramic-based baluns, lithium tantalate-based surface-acoustic-wave filters, discrete component crystal (XTAL) oscillators and digital physical-layer (PHY) chips that are based on different material structures (see figure).

This drive to maximize performance leads to a multichip solution, which unfortunately has a high-cost bill of materials. In addition to the associated difficulties of materials handling and assembly, the multichip approach frequently results in a module with a large footprint and high dc power consumption.

As a result, it is attractive to consider moving many of these circuit components on-chip to achieve a high level of integration and a small bill of materials. In an extreme case, an integrated radio would need only an antenna, a crystal, voltage supply bypass capacitors and host interface pull-up resistors. In reality, an integrated radio will likely still include external components, at least for many applications.

The candidate circuits for on-chip integration include filters, baluns, XTAL oscillators, T/R switches, power amplifiers and the digital PHY. When moving to a more integrated design, designers must make careful decisions regarding how to achieve on-chip performance, the actual performance required and which circuit components should remain external.

Generally, single-chip radio design allows certain opportunities that are not available in a traditional design. For instance, far better matching of on-chip devices allows balanced-signal circuit design, which enables common-mode rejection of interferers. This better matching also provides for better image-band rejection, which can reduce the requirements for external-RF or intermediate-frequency (IF) filtering.

The design of a mixed-signal single-chip radio also provides the opportunity to include complex digital filtering with very high performance. However, the dynamic range required by the analog-to-digital converters preceding the digital filtering must remain realistic, which implies that some on-chip analog filtering is also required to reduce adjacent channel-blocker levels.

Finally, the inclusion of adaptive cancellation techniques on-chip can further reduce any reliance on external RF and IF filtering. With the combined use of these complementary techniques, external filtering-with the exception of channel filtering-can often be eliminated.

The inclusion of on-chip spiral inductor and transformer geometries as well as metal-insulator-metal (MiM) capacitors enables baluns and crystal oscillators to be brought on-chip. Unfortunately, performance can be reduced as a result of the restricted quality factor (Q) achievable (due to ohmic losses) and from the limited isolation achievable (due to bulk substrate coupling) when these devices are realized on-chip. This translates into increased phase-noise levels for crystal oscillators and decreased balance for baluns. On-chip spirals also occupy large amounts of real estate, with an associated increased die cost. The decreased balance of baluns can be compensated for with adaptive techniques. Unfortunately, the higher oscillator phase noise cannot be reduced and must be acceptable to the overall performance requirement for on-chip crystal oscillators to be used.

While desirable, integrating the T/R switch on-chip presents some performance limitations, depending upon the chip process technology. As a general rule, the dynamic range and isolation achievable on-chip via st andard chip process technologies such as silicon and silicon germanium will be less than what could be provided by an external GaAs switch. The decrease in dynamic range can create intermodulation distortion for the transmitted signal, while the decrease in isolation can result in many diverse effects such as frequency pulling of the voltage-controlled oscillator in the synthesizer.

It is also very attractive to consider including the transmitter PA on-chip to reduce the overall bill of materials. Inclusion of a PA stage on-chip, however, brings associated difficulties and some significant design challenges. For instance, heat dissipation from the die becomes a problem as a result of low power-added efficiencies of realizable PAs. Low breakdown voltage, resulting from small feature-size technology, can also be a problem. In addition, parasitic coupling to other analog circuits on-chip can be substantial because of the high signal level. Substrate noise coupling from digital circuits can also be a problem .

Current PHY designs often consist of multiple analog and digital chips performing key RF and baseband functions. The industry is currently moving toward a single-chip PHY solution that incorporates all analog and digital functionality.

A true single-chip solution will not only include the analog functions discussed above but also the digital circuits of the physical layer. This kind of integrated solution can significantly reduce the total module complexity and cost. However, to realize low cost, the PHY layer should be realized on small-feature-size CMOS, such as 0.18 micron, or even smaller 0.13 micron in the future. On the other hand, RF analog circuits require reasonably high bias voltages to provide dynamic range and power, something small-feature-size CMOS does not provide. As a result, a compromise occurs, with larger-than-desired die size for the digital circuits and lower-than-desired voltage for the RF circuits.

Integration strategy
Before deciding on a single-chip radio des ign, engineers must first consider the capabilities of the target technology and target device. For instance, silicon, SiGe and GaAs all have different carrier mobilities, thermal conductivity, substrate resistivity and leakage currents. For example, Table 1 compares the major differences between the advantages of silicon and SiGe technologies, the closest-matching processes.

Between these two technologies, SiGe is preferable when designing low-noise amplifiers due to its lower noise, higher gain and wider stable temperature range, whereas silicon's higher breakdown voltage makes it better-suited for use in power amplifiers. On the other hand, the higher early voltage of SiGe allows high output resistance of amplifier stages to be achieved, which is also useful in the design of power amplifiers where robustness to variations in antenna load impedance is important.

After the material has been selected, the designer must contemplate the performance of the resident devices. Bipolar, heterojunction bipolar transistor, pseudomorphic high-electron-mobility transistor and CMOS devices all provide different transconductance, impedance-matching ranges, power consumption, linearity and noise characteristics for the devices. For instance, Table 2 compares the strengths and limitations of bipolar and CMOS devices, the two most popular technologies.

Bipolar devices are often preferred for the design of RF circuits because of their inherent characteristics of higher transconductance, easy impedance matching and higher voltage rails. On the other hand, CMOS devices provide better linearity for RF circuits than bipolar devices, which results in better intermodulation distortion performance for mixers and amplifiers. In general, CMOS devices are preferred for the design of digital c ircuits because of their small feature size and high yield.

While CMOS devices have attractive advantages, in light of reliability issues with currently available RF models and the challenges associated with low-transconductance, low-voltage rails and difficult impedance matching, there may be significant challenges to realizing an all-CMOS mixed-signal radio.

Process selection is extremely important, due in part to the ongoing foundry relationship, as well as to process-specific models. Process candidates for an integrated radio include BiCMOS process technology (bipolar for RF and CMOS for digital), or RFCMOS. Integration is improved via these processes by employing triple-well diffusions for isolation, thick top-metal layer for inductors, dual-oxide layers, MiM capacitors and high-resistivity resistors. The performance of passive components integrated using these features may be limited. For example, spiral inductors can only provide inductances in the range of 0.15 to 80 nanohenries, with Qs rare ly exceeding 12. Similarly, MOS capacitor Qs are limited to values of 20 / f(GHz) / C(pF), while MiM capacitors can only provide Qs four times larger.

Extra steps
When selecting a process, it is also important to compare power consumption, isolation, wafer costs and packaging alternatives. The inclusion of extra features on the die requires extra, or at least different, process steps, which increase the cost of fabrication.

To make good decisions about which components to incorporate on-chip and which to leave as external components, designers must carefully consider the available materials, devices and finally process, in light of the performance impact for each particular circuit component. Table 3 summarizes the challenges and difficulties of integrating the various candidate circuits on-chip.

While a single-chip solution may be attractive for a particular radio application, the impact on overall performance must be carefully considered. In the end, designers must carefully assess t he associated trade-offs. And, while for a number of applications it may be possible to effectively remove some of the external devices, for others it may not.

In these instances, designers will need to look to emerging circuit design techniques and new technologies to shrink the footprint, lower the cost and reduce power consumption for a multichip solution. Considering these issues, an integration strategy might comprise the following steps: