Chris Eddington - Synopsys
12/11/2012 11:37 AM EST
System simulators are becoming an increasingly important part of the FPGA and ASIC verification process, particularly for system-on-chips (SoCs) with performance-critical hardware accelerators and tightly-coupled embedded software. Cycle accuracy (CA) of the peripheral hardware is often a requirement or very desirable in many cases, especially if greater simulation performance over RTL simulation can be achieved. Some examples include:
- Detailed performance and utilization of system interconnect, based on the actual hardware implementation running with its embedded software.
- Implementation of low-level drivers and firmware, which require register maps and may rely on exact latency and flow control behavior of the peripheral.
- Software optimization, which can be particularly important for algorithm hardware accelerators, codec development, as well as in cases where hardware and software are tightly coupled and there is a critical overall performance goal in latency, throughput, etc. In such scenarios, estimates by ISS and TLM can be off by a factor of three, resulting either in wasted silicon or chips that cannot meet their required performance.
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