Shawn McCloud, Bryan Bowyer and Vikas Tyagi - Calypto
EETimes (1/7/2013 8:00 AM EST)
Low power is a central concern of digital design, especially for handheld and wireless devices, but also for servers and other computation intensive applications where the cost of cooling and packaging can be quite high. As a consequence, power optimization is an essential factor in meeting and improving quality of results as well as for optimizing performance and area.
Thus far, power optimization efforts have centered on RTL models and gate-level netlists, which are not sufficient for achieving optimal power savings. Optimizing for power should occur at all levels of design—from architecture to board. It is at the architecture, or electronic system level (ESL), where the potential for power savings are the greatest. Indeed, the opportunities for optimizing low power are significantly higher at the architectural level of abstraction—with as much as a 10X improvement over gate level optimizations. Yet, ironically, this is where low power methodologies and tools are the weakest. This deficiency drives the need for tools that not only allows designers to explore the best architecture for power at a higher level of abstraction but also automatically implements lower level transformations, like sequential clock gating, in the RTL produced.
The answer is found in the integration of high-level synthesis (HLS) and power analysis to create a new HLS product capable of optimizing across three dimensions - power, performance and area (PPA). HLS allows designers to synthesize different RTL architectures from C++ or SystemC electronic system level (ESL) models. The different hardware architectures are generated through user constraints which specify such things as clock period, resource limitations, IO protocol and the level of desired concurrency. Such a low power HLS solution can implement a generous range of low power techniques into synthesized RTL; including bit-width optimization, multiple clock domain partitioning, memory access minimization, resource sharing, frequency exploration, power gating, and clock gating.
In this article, we will discuss, in general, the ESL to RTL low power design flow, and then share the results of two case studies using real customer designs to evaluate the efficacy of a unique solution for ESL synthesis and power architecting.
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