MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3)
Getting your Zynq SoC design up and running using PlanAhead
Adam Taylor, EADS Astrium
EETimes (2/8/2013 11:22 AM EST)
The Zynq-7000 All Programmable SoC is the first of a new class of Xilinx devices that marry a dual-core ARM Cortex-A9 processor with programmable logic on a single chip. As such, the device offers a great leap forward in not only system flexibility, but also performance and integration. This system-on-chip platform does, however, require the FPGA engineer to consider a slightly different development path than is customary for logic-based FPGAs.
The good news is that development is not as difficult as you might think, thanks in large part to the availability of the Xilinx PlanAhead tool. Let’s take a closer look at the steps involved in generating a Zynq-7000 system that you can load via JTAG.
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