FPGA debugging techniques to speed up pre-silicon validation
Rajesh Udenia, Rohit Goyal & Neha Singh
EDN (February 7, 2013)
The increase in complexity of designs being prototyped on FPGAs has led to the increase in need for better debugging techniques. The design being prototyped on the FPGA may be used for performing validation, early software development, proof-of-concept etc. Thus, it becomes important that the focus remains on performing these tasks rather than trying to figure out whether an issue is caused due to a prototyping error.
Different debugging techniques may be required depending on the available design or type of task at hand. Adoption of proper debugging techniques can also reduce the cycle time for validation of design on FPGA.
This paper talks about some debugging techniques for FPGAs that can be adopted to speed up the validation process while at the same time highlighting some of their constraints. These debugging techniques can be used for the various challenges or issues faced during pre-silicon validation as discussed below.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs
- Reduce SoC verification time through reuse in pre-silicon validation
- Optimizing Up/Down Conversion with FPGA Techniques
- How to use snakes to speed up software without slowing down the time-to-market?
- Generating High Speed CSI2 Video by an FPGA
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Synthesis Methodology & Netlist Qualification
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)