By Amit Dey, Vikas Garg, Rahul Saxena, Shailesh Kumar
Signal and power integrity are important parameters in deep submicron technologies. For a SoC to perform as per the specifications, the above two parameters should be kept in check. As the circuits are being clocked at a faster rate to achieve higher computation capabilities, the power requirement is shooting up. The challenge is arising from the rise of number of transistors on a SoC, their reduced feature size, increased switching speed resulting into higher power density i.e. power consumption per unit area. This increase is being seen in average power as well as dynamic power consumption. Issues related to average power consumption are taken care of by building a robust power grid. However, the problem associated with dynamic power consumption requires separate attention.
While a MOS transistor is switching, its power requirement increases momentarily. This sudden surge in power requirement cannot be supplied by the power pads which are kept electrically very far from the MOS transistors. The grid would have a finite resistance ‘R’ and capacitance ‘C’ resulting in finite time constant ‘RC’ which would impede the immediate flow of charge from power pads to sinks.
This sudden surge of power requirement can only be fed locally by putting decoupling capacitors known as decaps which are nothing but MOS connected in such a way so as to work as a capacitor. As these capacitors are sitting in immediate neighborhood, the response time is very less and thus, the dynamic behavior of the circuit is improved considerably. The following figures suggest topologies for MOS capacitors.
Fig 1: NMOS Decap
Fig2: PMOS Decap
Fig 3: Stdcell Placement after decap addition
Figure 3 shows the placement of standard cells and decaps. The places left vacant after placing standard cells are filled by decap to improve the power integrity of Soc.
Fig 4: Layout for Decap
Fig 5: Layout for Filler
In Soc design cycle, during placement stage when the rows are filled with standard cells, the utilization of area is typically 40-80% which depends on the design, number of layers. Any attempt of increasing the floorplan utilization results in congestion and issues like design is not route-able or deterioration in noise profile resulting into timing failures. The rest of the area which are unutilized are filled with decap and fillers with decaps getting precedence over fillers. There are two diagrams shown below are the layouts of filler and decap. The Fig 4 shows the layout of Decap. It is clearly visible there are no metal layers in filler, but metal layers M1 in decap. Hence places where M1 is used for routing cannot be used for decap insertion and hence fillers are inserted. To enable more decap insertion instead of fillers we propose two flows one for ‘Placed and Routed’ design and another during normal Soc design cycle.
1) Methodology for ‘Placed and Routed’ design
In a ‘Placed and Routed’ design where decaps and fillers are already inserted, to increase the decap value we have to exchange already inserted fillers into decaps. To enable this M1 and VIA1 layer have to rerouted which can create potential shorts and spacing violation with M1 of decap when decap is inserted. To reroute the M1 and VIA1 routes, routing blockages of M1 and VIA1 layer are added as shown in the figure below. But before this we remove all the decaps and fillers from the design. After adding the routing blockages there will be numerous shorts and spacing violation between M1 and VIA1 layers and the routing blockages. To resolve these shorts the routes creating the violation are ECO routed, which causes the routes to reposition between the routing blockage as visible in the figure. Then the routing blockages are deleted. Now the decaps can easily be inserted without any DRC violation, as the M1 layer in decap are occupied in the region of previously added routing blockages. By this technique we get 10 - 20 % improvement in decap value.
Fig 6: Routing Blockages insertion
Fig 7: Flow Diagram for Placed and Routed Design
2) Methodology during Soc Design Cycle.
During Soc design cycle decap can be inserted post placement preroute stage. During pre route stage as there are no routing, so decap can easily be inserted without any DRC violation. Before routing as decaps are already placed, the routing in M1 will automatically route the M1 metal wires in between the space in M1 available in Decaps. In Fig 4 layout of decap is shown where it is clearly visible that middle portion of decap is devoid of M1, so the router will automatically route the M1 metal wires through the space available on Decaps. In this way the impact of decap cells will be considered from the initial phase of routing. Since optimization may be required after detailed routing and presence of decap at this stage may cause some DRC violation like cell overlap and it can also impact tool performance. To resolve this issue, here we are suggesting following two solutions:
- Make the placement status of decap placed before routing as “PLACED”, so during optimization tool will automatically delete the decaps from the places wherever buffer need to be placed or cell resizing need to be done.
- Delete the decap cells before each optimization run and reinsert decap cells after completion of optimization and before next detailed route run.
This technique allow 10-20% improvement in decap value.
Fig 8 Flow Diagram During Soc Design Cycle
Fig 9 Flow Diagram For Conventional
About the Authors:
Amit Dey(firstname.lastname@example.org): Working at Freescale Semiconductor, India as Design Engineer with 1.5 yrs experience in Physical Design.
Rahul Saxena (email@example.com): Working at Freescale Semiconductors, India as Principal Staff Engineer with 12 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design.
Vikas Garg (firstname.lastname@example.org): Working at Freescale Semiconductors, India as Staff Engineer with 8 years of experience in Physical Design.
Shailesh Kumar (email@example.com): Working at Freescale Semiconductors, India as Staff Engineer with 7 years of experience in Physical Design.