Adnan Hamid, Chief Executive Officer, Breker Verification Systems
EETimes (4/15/2013 10:53 AM EDT)
The electronics and semiconductor industries have relied on a modular building block approach since the dawn of time. By creating a limited number of interfaces and using these to connect components, this approach has enabled a fairly simple separation of the functional pieces. These distinct functional pieces are designed separately and integrated either at the chip, board or system level. This has often been compared to the “Lego” building-block approach.
Another common design practice has been to minimize the frequency of communications between the functional blocks because those interfaces generally have long latencies (compared to processing speeds) and are often the congestion points in a system. This also simplifies the integration process because it decreases the number of problems that can be created due to temporal interactions.
For many years, companies making the most complex system on chips (SoCs) have been quite successful performing the bulk of their verification at the block level. When the components are integrated, a small number of system-level tests are run to ensure that the blocks were properly interconnected.
This strategy, often called stitch and ship, is increasingly leading to failure because of growing complexity at the system level. In addition, increasing amounts of functionality are defined at this level. New verification strategies are required to bring system-level verification into the mainstream development flow.
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