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Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
Improving ASIP code generation and back-end compilation: Part 2
Wayne Wolf, Georgia Institute of Technology
Embedded.com (April 28, 2013)
Instruction selection becomes important when the processor has limited or irregular resources. Many DSPs have irregular register sets and operations, so instruction selection becomes very important for these machines. Limited or irregular processor resources are also influential when operations are performed. Instruction selection and scheduling may interact as a result of resource limitations.
As part of the FlexWare system, Liem et al. [7] developed an instructiongeneration system for ASIPs with irregular register files. Figure 3-8 shows the intermediate representation for programs, which includes both data and control flow aspects.
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