English
Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
A consumer reports methodology for IP
Piyush Sancheti, Atrenta
EETimes (5/7/2013 10:54 AM EDT)
As an SoC designer, you’re probably frustrated by how IP (3rd party and internal) can hinder your design getting to tapeout. After all, IP is supposed to be the cure-all for increasingly-complex SoC designs, right? However, it’s turned into a sometimes endless, difficult series of IP fixes. Why?
The answer is simple – it’s all about quality. Let’s think about this: the quality of today’s IP varies widely. SoC designers never know whether they will be able to use an IP block in multiple designs or if they will have a problem designing an IP block into just one design. SoC designers need better IP quality! They need a system to check the overall quality of the delivered IP, similar to a Consumer Reports analysis. And this analysis should enforce a quality standard so that the consumer has confidence that an IP block won't require difficult and time-consuming tweaks and fixes to work in the target design.
To ensure IP quality, design projects need to create such a Consumer Reports methodology. How do we get there? Here are some suggestions.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
- Methodology to reduce Run Time of Timing/Functional Eco
- Formal-based methodology cuts digital design IP verification time
- Deliver "Smarter" Faster: Design Methodology for AI/ML Processor Design
- New AI Computing in Consumer Electronics