Srinivas Velivala, Mentor Graphics
5/23/2013 5:16 PM EDT
The number and complexity of design rule checks (DRC) has always increased node over node, but as the semiconductor industry moves towards 20 nm and below, these increases are skyrocketing (Figure 1). The traditional DRC verification flow used by custom layout designers simply can’t provide the needed level of productivity when debugging DRC results at these advanced nodes. For example, custom layout designers are now confronted with complex checks that involve multiple factors, such as voltage-dependent design rule checks (VD-DRC) and double patterning (DP) checks.
In the long-established verification flow, the designer creates the layout in the design environment, writes out a GDSII file to disk, launches a DRC run, and then fixes the DRC errors in the design environment. Because the error correction and the validation of that correction are separate processes, designers must usually perform multiple iterations of this check-correct-verify process before they achieve signoff DRC closure.
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