Biswaprakash Navajeevan & Vivek Singh, Freescale
EDN (June 18, 2013)
Striving to achieve an integrated user experience, today’s devices are getting crammed with loads of features which operate on voluminous data traffic over various interfaces. For efficient processing of these data, faster memories offering high bandwidth are the need of the hour. In spite of availability of many different kinds of memories, Double Data Rate (DDR) memories maintain their dominant position when it comes to offering large amount of dynamic random access storage with high bandwidth data transfer interface. These types of memories are called Double Data Rate as they offer double the performance compared to the Single Data Rate memories by allowing two data transactions per memory clock.
A typical DDR memory is arranged in banks having multiple rows and columns along with pre-fetch buffers. For any data transaction, the memory address is split into bank address, row address and column addresses. The performance advantages of the DDR memory are mainly due to its pre-fetch architecture with burst oriented operation; where a memory access to a particular row of a bank causes the pre-fetch buffer to grab a set of adjacent datawords and subsequently burst them on IO pins on each edge of the memory clock, without requiring individual column addresses. Thus the higher the size of pre-fetch buffers, the higher is the bandwidth. Higher bandwidth is also achieved by creating modules with multiple DDR memory chips.
DDR memories require specific power up and initialization sequence prior to their operation. Before any read or write transaction, a particular row of a bank needs to be activated/opened (which essentially activates and amplifies the signals from that row) and after the end of the transaction it is pre-charged/closed if no further access to the row is needed. The DDR memories need to be periodically refreshed so that they don’t lose any of their contents.
The size of pre-fetch buffer is 2n (two datawords per memory access) for DDR memories, 4n (four datawords per memory access) for DDR2 memories and 8n (eight datawords per memory access) for DDR3 memories; where n is the size of IO interface typically 4, 8 or 16. These pre-fetch schemes attribute their effectiveness to the principle of spatial locality.
With these basic understandings, the specific features and functionalities of DDR3 memories are further discussed in the following sections.
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