With pressure to reduce both cost and time-to-market, many chipmakers are turning to intellectual property (IP) providers for existing, pre-verified hard and soft IP. While this approach greatly reduces the risk of a new design (including both cost and time-to-market), it presents a unique set of its own issues. Awareness of these issues, and being prepared to solve them, is the key to success in IP integration. Compared to hard IP, soft IP is more flexible; it can be fabricated in different foundries, and optimizations can be made to the IP to better fit the product.
The success of IP integration starts with choosing a solid IP provider. A good IP provider is a solution provider, one that offers a solid solution package that offers not only quality IP, but also a support system including detailed documentations, competent field application engineers (FAEs) and timely engineering support.
A solid deliverable package should in clude RTL code, verification environment, synopsis scripts, place and route guidelines, and supportive documentations. For microprocessor or programmable DSP vendors, tools support is crucial and should include assembler, compiler, OS, library functions and application software. Additionally, a generic hardware development system could be very helpful for prototyping new products for the IP user.
While the quality of the IP is difficult to measure at first glance, asking about an IP vendors' release procedure, verification process and verification coverage will present an idea of how important verification and quality control is to the vendor, thereby reflecting the quality of the IP.
Once satisfied with the company's delivery package and product quality, the IP user should try to acquire a designated support person. Speak with that person to test out his/her technical capability, maturity and dedication. Since this will be the main person supporting the user, make sure the person is easy to work with, knowledgeable, and, most importantly, dependable. Some IP vendors prefer to have the FAE as the main point of contact while providing different people for support as issues come up. Make sure the FAE is not only technically sound enough to understand the issues, but also resourceful and well organized to follow up on the issues.
The keys to identifying a solid IP vendor:
-There is a complete delivery package.
-There are sufficient software and tools.
-The vendor has a solid quality control and verification process.
-There is a standard support structure.
-The vendor has competent support engineer or FAE with strong knowledge of product.
-If you are still not sure, ask for reference customers.
While the goal of purchasing IP is to reduce the engineering effort, the process of integrating IP is not a "drop and done" process it requires a lot of engineering skills and effort for it to be successful. Therefore, it i s important to have somebody on the team dedicated to the IP integration.
First, the functionality of the IP needs to be fully understood, so that the whole chip can be architected accordingly. While the sales brochure may say the IP could do everything, it is important to check with the support engineer to fully understand the functionality and performance limitations of the IP. Most IP vendors make their soft IP configurable, so it can be reused in different applications for better performance/cost trade offs. This is a very solid IP reuse strategy. To make the right configuration decision, the customer needs to fully understand the trade-offs of different configurations. This is when a competent support engineer becomes very important to avoid a costly mistake in the architecture.
Second, the RTL structure must be fully understood, including the number of clock domains, the relationship between the clocks, gating clock issues, reset signal structure and potential testability issues. M ake sure the IP follows the synthesis design methodology closely. Mark all asynchronous reset signals that do not come from a flip-flop and ask for an explanation why it was necessary. Mark all asynchronous interface signals and make sure they have been carefully considered. IP vendors usually provide this information.
Third, verify the IP again. Even though all IP vendors verify their IP, it is still very important for the users to re-run the vendors verification vectors to make sure there are no files missing in the delivery. Most importantly, run a thorough verification with the integration logic around the IP. IP integration is a project involving different engineers in different teams from different companies, prone to the classic engineering problem: most bugs come from design and human interfaces. Fully verify the IP in a higher hierarchical level (to prevent most of the potential communication problems) while, at same time, double-checking the initial assumptions made about the IP. All of these are good engineering practices, even in an internal project, and they become even more important when external IP is involved.
If the original IP does not follow the synthesis design methodology closely, for example having combinational logic in the reset, place and route could be challenge. Ask the IP vendor for place and route guidelines and prime time scripts.
So, to successfully integrate soft IP, it is essential to:
-Identify a contact person within the company who is quick to respond and resourceful.
-Fully understand the function and configuration of the IP.
-Always run simulations on the IP. Do not make any assumptions, ambiguity can only hurt. When there are questions, ask the vendor.
-Understand the clock structure and requirements.
-Understand the test requirements.
-Understand place and route requirement. Ask for primetime constraint scripts.
-Always run gate level simulations.