Today's multimillion-gate SoC designs consist of mixed intellectual property CPU cores, memory, ADC/DAC and more that represent multiple levels of design abstractions, such as RTL, gates, transistors and analog behavioral models. A large amount of the IP in these complex designs is called "Big D" (large digital) because it must be verified at the gate or RT level using digital simulation techniques. An equally large amount of the IP is called "Big A" (large analog) because it must be verified at the transistor level using analog techniques. The task of verifying such Big D, Big A IP in an integrated multi-level, mixed-signal (MLMS) SoC environment is a challenge that demands a next-generation MLMS simulator.
At the same time, the convergence of wireless applications, personal computing and entertainment systems continues to drive the need for more powerful, complex and highly integrated IC design and manufacturing technolo gies. Meanwhile, the demand to lower cost and power consumption in ICs plus the ever shrinking market window force designers to pack an entire system on a single chip, and take full advantage of available silicon intellectual property (SIP).
The SIP, either developed internally or acquired from a third party, typically consists of one or more processor cores, memory, and logic, as well as RF and other analog blocks. Today, more than 50 percent of all IC designs use SIP, working with the SoC methodology that yields the smallest chip size and optimum power consumption.
Needless to say, designing such complex chips is a daunting task. Equally challenging is the task of ensuring that chips meet functional, timing and power specifications and work right the first time. According to an independent market study, at 0.13 micron, up to 45 percent of all designs will require at least one additional full mask-set iteration, costing close to $1 million per set. If you factor in th e potential loss due to missing the market window, the cost becomes enormous.
Traditionally, different teams verified the digital and analog portions of an SoC design. For instance, the digital design team would follow the top-down design approach, using either Verilog and/or VHDL simulators to verify the design first at RTL and then at the gate-level, after logic synthesis. The analog design team, however, would start from the bottom up using a SPICE simulator to verify the design at the transistor level. The teams would verify IP blocks based on whether they were digital or analog and on the block's design abstraction level (RTL, gate-level, SPICE or Verilog-A netlist). Then, the integration team usually performed the final functional verification of the entire SoC at the very end of the design cycle after the design had been stitched together. Since it was impossible to verify the entire design at the transistor level with SPICE, a digital approximation of transistor-level blocks was often used to allow the design to be verified using digital simulators.
A main concern with this traditional approach: integration verification occurred too late in the design cycle to allow for the efficient repair of any integration errors that were discovered. Also, reliance on separate simulators introduced inherent inaccuracies. These deficiencies in this approach often resulted in costly and frequent design re-spins.
In the last decade, commercial EDA tools have emerged to enable co-simulation of digital and analog functions using Verilog/VHDL and a SPICE-based simulator. These co-simulation tools were designed to handle "Big D, Little A" types of designs. But these tools have lacked the capacity and performance to handle today's "Big D, Big A" variety of SoCs, which have equally large portions of digital and analog blocks. A next-generation simulator for SoC integration verification is, therefore, required to handle these complex designs.
A next-generation solution for B ig D, Big A simulation has emerged that tightly integrates high-performance Verilog/VHDL with a high-performance SPICE simulator to deliver a single kernel simulator. It supports design abstractions in RTL, gate, and SPICE so integration verification can be performed at all phases of the design cycle. It also supports analog behavioral modeling such as Verilog-A and C models, so that a top-down, analog verification method can be deployed. A key benefit is the ability to verify the entire system at the specification level to allow better architecture and IP selection.
In addition, it offers the flexibility to handle the verification of a variety of embedded IP, such as a Verilog-based IP with a SPICE netlist or vice versa. And, it supports multi-level mixed signal verification of "Big D, Big A" SoCs such as high-performance designs with built-in PLL circuits.
Synopsys' NanoSim, integrated with VCS, is an example of this next generation in Big D, Big A simulation. With support for SPICE ne tlist formats, the tool adopts into any transistor-level verification flow and addresses the multi-level mixed signal verification needs.
As process technology continues to advance below 100 nanometers, the cost of leading edge SoC design plus time-to-volume pressure will no doubt continue to rise. To ensure that designs work right the first time, a next-generation simulator for SoC integration verification is required. This simulator must be able to handle very large digital and analog blocks effectively, and simultaneously simulate a wide variety of design abstractions from RTL, gate, transistor and analog behavioral models.