Ateet Mishra, Amol Agarwal, and Abhishek Mahajan (Freescale)
EDN (August 13, 2013)
With the fast developing technology, the complexity of design is increasing day by day. To meet lower technology challenges and to achieve good silicon yield, SOC design flows have been enhanced and have introduced more number of design implementations steps. With every implementation step which takes design towards realistic working silicon, SOC design timing performance degrades due to various factors which were not apparent at previous implementation step. Thus it is very important to have a right estimate of design frequency since first stage of design implementation. The important parameter which makes it possible are called Design Margins.
Design Margins are the extra pessimism introduced in terms of design uncertainty which covers the expected timing hit of every stage in implementation cycle so as to achieve targeted frequencies well in time. It is very much required to have a right estimate of design margins.
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