Ron Press, Mentor Graphics
EDN (August 19, 2013)
Hierarchical test is a methodology that lets you perform most of the DFT work at the block level instead of at the flattened top level of the design. It is not a new approach. In fact, I’ve seen hierarchical DFT methodologies for over 15 years. What is new is the amount of automation available for making blocks independently testable and the very useful ability to directly retarget the patterns from the block to the top level.
Traditional flat ATPG is simple because the automatic test pattern generation session is only performed on the single, final, netlist. Flat ATPG implies that the design is complete and the ATPG session is performed on the entire design at the same time as one “flat” view. However, for designs that are too big to perform flat ATPG, test engineers often turned to hierarchical DFT to manage compute resources and runtimes. The basic hierarchical DFT methodology involves designing cores with scan wrappers so that they can be tested independent of their context in the top-level design.
Then at the top level, the block is accessed in a test mode that routes all IC test ports to the block scan channels for ATPG and testing. This not only helps with compute resource memory but also improves the run time, since the blocks not being tested can be omitted from the design view used for ATPG of the block under test. In addition, hierarchical test lets you take into consideration the variations of pattern types, pattern counts, etc. between blocks.
Even hierarchical DFT without much automation support can give you over two times improvement in test application time. But now, newer automation capabilities have improved hierarchical test significantly, and make it an attractive option for many designs. New DFT tools can create graybox models of the blocks, which act as very small block images that can be used for top-level test rules checking and for interconnect test between the blocks.
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