Anil Panchal, Sr. Engineer, eInfochips Ltd
How to verify the on chip system which has noisy sub components such as digital Filters?
Description of Problem:
Digital systems, which implement various protocols like PCI Express, SONET, Ethernet and OTN; maintains data integrity in and out of the system. Thus verification of such systems involves a score board which checks the data integrity from input to output. These systems do not have noisy components in its implementation. The logic in such system does not implement mathematical algorithms.
In digital signal processing, the logic is implemented through mathematical algorithms. And hence the input and output does not match either due to precision problems, in accurate modeling and synchronization issues between design and reference models.
Figure: Design adds the noise
Source of Nose in simulation:
The source of noise in simulation is limited number of bits used in the hardware to implement basic function such as addition, multiplication, generation of Sine Wave etc. Certain components like digital filter have attenuation on specific frequency bands. Additionally, it is always not possible to model the reference model exactly as the design under test. It may not be possible to do score boarding on sample by sample basis.
In few cases detailed micro architecture definition exist. So you may try to model exact micro architecture, but the internal details such as rounding, saturation and initial state (initial phase) may be arbitrary. This will be a issue in predicting the sample that matches with design and stays synchronized with design.
The efforts in synchronizing the verification environment with the design are time consuming, complex and difficult to maintain and manage.
After knowing the fact that the design adds the noise at the output, there must be margin specified by design or designers that the noise level should be in certain range.
The standards to test this kind of design may include a Sine Wave generator at the input. The Sine wave shall pass through the design. Finally the data samples out of the design can be sent to MATLAB script for the analysis of the data received from the design. The script can calculate the power of frequency components present at the output of the design. If the noise level matches minimal margin expected out of the design, the test will be Pass.Figure: Flow of Solution
- No synchronization required between design and verification environment for checking
- The precision issues between design and verification will be instead described by margin instead of 1:1 matching
- For the verification of Filters, this can avoid need of writing complex codes as a reference model.