Etienne Racine, Mentor Graphics
EDN (October 2, 2013)
3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional, single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations. EDA tools must make this definition step as simple as possible, while ensuring it can be reused across designs and over time. We also see that traditional test algorithms are less efficient on DRAMs, so they must be reconsidered in a 3D-IC context.
Comparing SRAMs and DRAMs
For testing SRAMs, EDA flows can automatically detect embedded memories and assign each instance to a specific BIST controller. This assignment depends on the chip architecture and includes user-defined parameters such as test time, power consumption limits, etc. A BIST engine typically tests many SRAMs in parallel through a simple interface (e.g., multiplexors).
To test external DRAMs used in 3D-ICs, the situation is, however, quite different. It often requires a new IP block, called the PHY (physical interface), which sits between the core logic and the memory. This PHY is reasonably complex and may also contain its own embedded I/O. A single BIST controller is then dedicated to test that specific PHY.
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