Chris Loberg, Tektronix
EDN (October 25, 2013)
The PCI-SIG, the organization responsible for PCI Express, and the MIPI Alliance, the organization behind M-PHY, are in the process of finalizing a new M-PCIe specification that combines the low-power, flexible signaling electrical performance of M-PHY with the interoperability and I/O functionality of PCIe. For designers who in many case are still coming up to speed on the latest PCIe 3.0 and M-PHY technologies, this new M-PCIe technology will present a number of unique test and measurement challenges. Here we highlight some of the important elements of the emerging specification as it relates to design and test, and outline key considerations as this standard gains acceptance.
The typical desktop or laptop PC has a PCI Express bus at its core and has been the computing platform of choice for productivity and entertainment for the last 20 years or so. 350 million were sold in 2011. Now however, after several quarterly declines in PC sales and gloomy forecasts for the future, it’s clear the salad days are over for PCs as mobile devices like smartphones and tablets take over.
But it’s hard to imagine the PC fading away without a fight. Instead what’s likely to happen is the emergence of a new class of device that combines the performance and rich functionality of a PC with the portability and battery life of mobile. Such a compromise-free device will incorporate backbone PC interfaces such as USB and PCIe, bringing the massive PC ecosystem along for the ride into the fast-growing mobile universe.
The first step occurred with the release of the SuperSpeed Inter-Chip (SSIC) specification in June 2012, which enabled USB 3.0 to connect chips using M-PHY physical interface. A similar step now is taking shape with M-PCIe efforts to combine the upper layers of PCIe with M-PHY to bring PCIe hardware and software functions to mobile devices. As shown in Figure 1, the multi-layered M-PHY specification offers a single standard, powerful enough to address existing and future mobile device requirements, and yet is flexible and configurable enough to accommodate a range of technologies.
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