English
Can Hardware-Assisted Verification Save SoC Realization Time?
Srivatsan Raghavan, Senior Architect, Vayavya Labs
EETimes (11/8/2013 10:00 AM EST)
I recently attended Cadence-Live in Bangalore to learn about the latest and greatest in verification technologies. As expected, many of the sessions were geared towards System-on-Chip (SoC) verification using formal and simulation techniques. The main draw was the hardware-assisted (HA) verification session track. Yes, I use the word "hardware-assisted" since the word "emulation" is overloaded, confusing, and a misnomer.
It looks as if the "Big Three" EDA vendors are gearing up for the next battle to capture the SoC verification market. Hardware boxes such as Palladium have been around for years. So, why the sudden buzz? My take? Two factors as follows
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Reduce SoC verification time through reuse in pre-silicon validation
- An Effective way to drastically reduce bug fixing time in SoC Verification
- Expanding emulation's reach with virtual devices
- SoC realization: Finally the "Killer App" that will allow EDA to grow again?
- Surveying the hardware-assisted verification landscape