English
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
Handling Asynchronous Clock Groups in SDC
Sanjay Churiwala & Balachander Krishnamurthy, Xilinx
EETimes (11/15/2013 04:40 PM EST)
Introducing CDC
Most SoC designs in today's world employ multiple clocks and commonly have many clock domains. As data crosses from one clock domain to another within the design, the potential for metastability problems arises due to asynchronous clock domain crossings (CDCs).
Figure 1: An asynchronous crossing with simple double flop synchronization.
In Figure 1, there is an asynchronous CDC for the data going from flop F1 (clocked by C1) into F2 (clocked by C2), assuming that C1 and C2 are asynchronous with respect to each other.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Xilinx, Inc. Hot IP
Related Articles
- Asynchronous Logic: large CMOS devices without a clock tree
- Handling the Challenges of Building HPC Systems We Need
- Verifying Dynamic Clock switching in Power-Critical SoCs
- Optimization of Crosstalk Delta Delay on Clock Nets
- Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- PCIe error logging and handling on a typical SoC
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)