Sanjay Churiwala & Balachander Krishnamurthy, Xilinx
EETimes (11/15/2013 04:40 PM EST)
Most SoC designs in today's world employ multiple clocks and commonly have many clock domains. As data crosses from one clock domain to another within the design, the potential for metastability problems arises due to asynchronous clock domain crossings (CDCs).
Figure 1: An asynchronous crossing with simple double flop synchronization.
In Figure 1, there is an asynchronous CDC for the data going from flop F1 (clocked by C1) into F2 (clocked by C2), assuming that C1 and C2 are asynchronous with respect to each other.
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