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NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Platform-Based Design: What is Required for Viable SoC Design?
by Bob Altizer, Larry Cooke and Grant Martin
SoC Paradigm Change
When the Virtual Socket Interface Alliance (VSIA) began promoting IP block reuse in 1996 (or as VSIA calls it, Virtual Component (VC) reuse), state of the art chips were about 1 million gates. If each VC were 50,000 gates in size, there would be 20 blocks to integrate together. Today the state of the art is about 40 million gates and by the same measure there would be 800 blocks to integrate. But that is only a small part of the problem. Six years ago the chip was still a component in the system, but next generation chips are the system, with complex communication sub-systems, multiple processors, and their embedded software, all on a single piece of silicon.
SoC Paradigm Change
When the Virtual Socket Interface Alliance (VSIA) began promoting IP block reuse in 1996 (or as VSIA calls it, Virtual Component (VC) reuse), state of the art chips were about 1 million gates. If each VC were 50,000 gates in size, there would be 20 blocks to integrate together. Today the state of the art is about 40 million gates and by the same measure there would be 800 blocks to integrate. But that is only a small part of the problem. Six years ago the chip was still a component in the system, but next generation chips are the system, with complex communication sub-systems, multiple processors, and their embedded software, all on a single piece of silicon.
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