Dataquest predicts automation of RTL
Dataquest predicts automation of RTL
By Richard Goering, EE Times
June 10, 2002 (2:36 p.m. EST)
NEW ORLEANSThe "automation of RTL" will be driven by the silicon virtual prototype and the intelligent testbench, according to Gary Smith, chief EDA analyst at Gartner Dataquest. Speaking Sunday (June 9) at Dataquest's annual briefing prior to the start of the Design Automation Conference, Smith also took an extremely skeptical view of platform-based design.
In an updated forecast of EDA software revenues, Smith said Dataquest projects 2002 revenues of $3.045 billion, up from $2.710 billion last year. "We're shooting for 12 percent growth this year, but it's still tough out there," he said.
Electronic design automation vendors face four main challenges, Smith said: the IC implementation toolset; the silicon virtual prototype; the intelligent test bench; and electronic system (ES)-level design tools. Smith didn't spend much time talking about the RTL-to-GDSII IC implementation toolset, he said, because Cadence Design Systems, Synopsys, and Magma Design Automation have that market "pretty much wrapped up."
The silicon virtual prototype is moving forward with the entry of companies such as Tera Systems, InTime, Icinergy, and Magma Design Automation into this market, Smith said. He called the silicon virtual prototype "the design cockpit for all future designs," and said it will provide the "reality" that ES-level tools have thus far lacked.
Silicon virtual prototyping is significant, he said, because it enables RTL signoff, which Smith identified as the most popular issue at DAC this year. "This is the new back end this is the implementation flow," he said. "It changes the entire business structure of the EDA industry."
Also important to the new, automated RTL flow is the intelligent testbench, which will allow users to devel op testbenches at the ES level, partition a design, and then automate the verification flow, Smith said. The building of this intelligent testbench will drive "serious consolidation" in the verification market over the next year, he said.
"There are 81 functional verification vendors today," he said. "At next year's DAC, there will be some reasonable number, like four."
Between 2002 and 2005, Smith said, "third-generation" ES tools will evolve. The first generation was domain specific, and the second failed in its attempt to merge datapath and control, he noted. And there's still an obstacle. "The problem today is that hardware and software don't talk to each other, and you can't do ES-level designs until we figure out how to make that happen," he said.
Looking more deeply at this problem, Gartner Dataquest analyst Daya Nadamuni identified three different design styles: system-on-chip (SoC), where the competitive advantage is hardware; embedded, where the competitive advantage is soft ware; and component-based, where the main concern is cost and time-to-market.
Nadamuni noted that software design is model-based, while hardware design is language-based. "The key is to find a design style that absorbs both," she said. "How do we resolve incompatibility between the two design flows? Recently, people have pointed to platform-based design as a panacea to automation of the ES level."
But Smith then returned to the podium to throw cold water on that notion. Platform-based design, he said, is a "buzz term with no set definition," although the original notion seems to be one of a fixed architecture.
Smith said that development of a platform takes 18 months to two years, is very expensive, and poses a big verification challenge. Return on investment is a problem, because the platform must be viable for three years. Thus, he said, platform-based design fits into the embedded world, not the SoC world, and even then for relatively few applications.
"Platforms are not a bad idea, but they certainly aren't going to solve the SoC problem," Smith said. "The idea in this business is to make money and in many cases, platforms will make you broke."
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