Decreasing parasitic capacitance in IC layouts

Gagan Kansal, Ajay Sharma, Imam Raza (Freescale Semiconductor)
EDN (January 04, 2014)

As the Semiconductor industry is growing so does the density of devices on chip. With the increasing density and decreasing spacing rules, the most significant effect that takes birth is parasitic. Parasitics can be of resistance or capacitance types, both have to be handled carefully. In this paper we will discuss parasitic capacitance.

In VLSI applications the parasitic capacitance between signal lines can deplete our whole design. At low frequencies parasitic capacitance can usually be ignored, but in high frequency circuits it can be a major problem. For example, in amplifier circuits with extended frequency response, parasitic capacitance between the output and the input can act as a feedback path, causing the circuit to oscillate at high frequency. These unwanted oscillations are called parasitic oscillations.

The parasitic capacitance arises from an electrical coupling between one signal line and another signal line or a signal line and the substrate. In some designs it becomes mandatory for us to reduce the parasitic capacitance of a particular net with respect to other signal. Now how it can be done? What are the different ways to be approached for that? We will discuss all these methods in this article.

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